NOT Gate Research Articles

Optimizing the Geometry of Chiral Magnetic Logic Devices

We investigated how geometry affects chiral magnetic logic devices, using micro-magnetic simulation. The logical NOT gate in the device was operated by current-induced domain wall (DW) motion in perpendicularly magnetized nanowires with a locally modulated in-plane magnetic anisotropy (IMA) region, where the up-down DW is switched into a down-up DW by current. We modulated the width of the nanowires as well as the length of the IMA region and found that an optimized geometry exists which depends on the Dzyaloshinskii-Moriya Interaction. Integrating the optimized NOT-gate, we then demonstrated NAND or NOR logic operations. Our results provide design guidelines for the magnetic logic device, paving the way to functional magnetic logic-inmemory devices.

Magnetic field- and light-driven spin molecular logic gates: A first-principles study

We design a novel combinational molecular device consisting of a planar four-coordinate Fe molecule and a 15,16-dinitrile dihydropyrene/cyclophanediene molecule with carbon nanotube bridge and electrode, and investigate its spin-polarized transport properties using density functional theory and non-equilibrium Green's function formalism. The results show the spin-polarized currents are strongly dependent on the magnetic field and light modulations. Perfect spin filtering and large switching effects are realized. The results are explained by spin-resolved transmission spectra, energy levels of molecular projected self-consistent Hamiltonian orbitals, and their spatial distributions. Based on the spin-polarized transport properties, we propose spin molecular AND, OR and NOT gates.

Design of Plasmonic NOT Logic Gate Based on Insulator – Metal – Insulator (IMI) waveguides

In this work, all-optical plasmonic NOT logic gate was proposed using Insulator-Metal-Insulator (IMI) plasmonic waveguides Technology. The proposed all-optical NOT gate is simulated and realized using COMSOL Multiphysics 5.3a software. Recently, plasmonic technology has attracted high attention due to its wide applications in all-optical signal processing. Due to its highly localization to metallic surfaces, surface plasmon (SP) may have huge applications in sub wavelength to guide the optical signal in the waveguides which results in overcoming the diffraction limit problem in conventional optics. The proposed IMI structure is consist of a dielectric waveguides plus metallic claddings, which guide the incident light strongly in the insulator region. Our design consists of symmetric nano-rings structures with two straight waveguides which based on IMI structure. The operation of all-optical NOT gate is realized by employing the constructive and destructive interface between the straight waveguides and the nano-rings structure waveguides. There are three ports in the proposed design, input, control and output ports. The activation of control port is always ON. By changing the structure dimensions, the materials, the phase of the applied optical signal to the input and control ports, the optical transmission at the output port is changed. In our proposed structure, the insulator dielectric material is glass and the metal material is silver. The calculated contrast ratio between (ON and OFF) output states is 3.16 (dB).

Phase sensitive, all-optical and self-integrated multi-logic AND, OR, XOR, and NOT gates

The design and simulation of all-optical and self-integrated primary logical AND, OR, XOR and NOT gates based on phase sensitivity of spatial optical solitons have been reported. By tuning the phase of incident solitons into a bulky nonlinear Kerr medium and interaction between the phase tuned solitons, the self-integrated logical gates are achieved simultaneously in a 50 μm long distance by one setup. These are the advantages in the application and design of integrated circuits. In addition, the proposed logical gates can be cascaded and the logical AND and XOR gates can simultaneously have two outputs. The simplicity of constructing, simultaneous functions with one setup, the possibility of integrating, high sensitivity and fabrication ease are the advantages of the proposed logical gates and may be a good candidate for the future of integrated photonic computational circuits.

Nanoscale Optical Logic Circuits by Single-Step FRET

We propose a method for implementing nanoscale optical logic circuits via single-step Forster resonance energy transfer (FRET). Use of single-step FRET enabled circuits with simple design and high expandability. Two kinds of FRET gates, a YES gate and a NOT gate, were used to modulate fluorescence output signals based on light inputs. Various logic circuits could be implemented by connecting FRET gates on a DNA structure. The experimental results demonstrated that FRET gates for two kinds of input lights were constructed, and that logic circuits executing the AND and OR operations produced fluorescence signals as outputs.

Advanced Improvement in Speed of Operation of 3-Stage CMOS Ring Oscillator Clock Generation using CPG

The Ring oscillator is a member of time delay Oscillators. In this Ring oscillator it uses odd number of inverters and has a gain greater than one. In normal Ring Oscillator architecture the performance is very low due to power gating mechanism. By using CPG technique the performance is increased and also utilizes low power for operation. This Ring oscillator by using CPG technique is affected by pressure and temperature variations. By using 3-stage CMOS ring oscillator the efficiency and performance is increased. In CMOS Ring oscillator power supervision (PS) and efficiency is increased. Most of the architecture is planned for cut back the ability within the IPs to provide power gating, with the task of falling system level control gating. In this CMOS Ring oscillator the output of each NOT gate is given to next stage in order to improve the system latency. For CMOS Ring oscillator, there is no output is given to system, but Reset pulse will drive the entire architecture. In CPG power of the device will change in cyclic manner, device will be ON and OFF over small duration of time. By this proposed method over all power consumption and speed of operation is increased.

XOR Gate Design Toward a Practical Complete Set for DNA Computing

Practical design of the XOR gate is an important milestone in the field of DNA computing. In this study, we aim to develop an enzyme-free XOR gate driven by a toehold-mediated strand displacement mechanism possessing the true detection property. The advantages of our design are as follows: dual-rail logic is not required, the explicit use of the NOT gate is avoided, the circuit structure is simple, and the design is achievable with fewer DNA strands than that designed by the combination of four NAND gates. A rational circuit design is performed and the dynamic behaviors of the biochemical reaction and the secondary structures of DNA strands are confirmed by computer simulation. In particular, both the domain-level design technique with G-T mismatched base pairs and base sequence-level fine-tuning are successfully achieved to alleviate the performance degradation arising from unintended and leaky reactions present in the circuit. The validity of the XOR gate design is confirmed by experimental studies.

Kondo-free mirages in elliptical quantum corrals

The quantum mirage effect is a fascinating phenomenon in fundamental physics. Landmark experiments on quantum mirages reveal atomic-scale transport of information with potential to remotely probe atoms or molecules with minimal perturbation. Previous experimental investigations are Kondo-effect based; the quantum mirages appear only near the Fermi energy. This strongly limits the exploration of the mechanism and potential application. Here we demonstrate a Kondo-free quantum mirage that operates in a wide energy range beyond Fermi energy. Together with an analytical model, our systematic investigations identify that the quantum mirage is the result of quantum interference of the onsite electronic states with those scattered by the adatom at the focus of elliptical quantum corrals, where two kinds of scattering paths are of critical importance. Moreover, we also demonstrate the manipulation of quantum mirages with pseudo basic logic operations, such as NOT, FANOUT and OR gates.

All-Optical Switching and Multiple Logic Gates Based on Hybrid Square–Rectangular Laser

All-optical switching and multiple logic gates are experimentally demonstrated using AlGaInAs/InP hybrid square-rectangular lasers. Controllable bistability induced by saturable absorption in the square microcavity is achieved around the threshold with the square cavity in an open circuit state. Based on the bistability, all-optical switching operation is realized by injecting set/reset optical signals with the wavelengths around the lasing mode of 1529.9 nm and another high-Q mode at 1560 nm. Furthermore, mode competitions between three resonant modes around 1541 nm with an interval of 1.2 nm are used to realize all-optical multiple logic gates of NOT, NOR, and NAND functions under low-power optical pulses, with injecting currents to the square and rectangular sections. The static extinction ratio of 34, 40 and 24 dB are obtained for NOT, NOR, and NAND gates, respectively, and the dynamic extinction ratio over 10 dB of NOT function at 15 Gb/s, NOR and NAND functions at 2 Gb/s are demonstrated. With the merits of multifunctional operations, large optical injection wavelength tolerant ranges, low power consumption, small footprint and suitability for on-chip integration, the device offers a potential solution for all-optical signal processing in photonic integration circuits.

A Quantum Control NOT Gate Based on Four-Wave Mixing in a Cavity for Photonic Qubits with Orbital Angular Momentum

Photonic qubits with angular momentum states interacting in a medium with Kerr-type nonlinearity in a cavity are considered. The use of a quantum logic gate (a controlled NOT gate) in the process of four-wave mixing on such qubits is considered. A theory of the functioning of this gate is constructed using the input/output formalism. The conditions for matching the parameters that must be realized for the effective operation of the gate are obtained.

Bottom-Gate Approach for All Basic Logic Gates Implementation by a Single-Type IGZO-Based MOS Transistor with Reduced Footprint.

Logic functions are the key backbone in electronic circuits for computing applications. Complementary metal‐oxide‐semiconductor (CMOS) logic gates, with both n‐type and p‐type channel transistors, have been to date the dominant building blocks of logic circuitry as they carry obvious advantages over other technologies. Important physical limits are however starting to arise, as the transistor‐processing technology has begun to meet scaling‐down difficulties. To address this issue, there is the crucial need for a next‐generation electronics era based on new concepts and designs. In this respect, a single‐type channel multigate MOS transistor (SMG‐MOS) is introduced holding the two important aspects of processing adaptability and low static dissipation of CMOS. Furthermore, the SMG‐MOS approach strongly reduces the footprint down to 40% or even less area needed for current CMOS logic function in the same processing technology node. Logic NAND, NOT, AND, NOR, and OR gates, which typically require a large number of CMOS transistors, can be realized by a single SMG‐MOS transistor. Two functional examples of SMG‐MOS are reported here with their analysis based both on simulations and experiments. The results strongly suggest that SMG‐MOS can represent a facile approach to scale down complex integrated circuits, enabling design flexibility and production rates ramp‐up.

Integrable all-optical NOT gate using nonlinear photonic crystal MZI for photonic integrated circuit

A silicon photonic crystal (PhC)-based nonlinear Mach–Zehnder interferometer (NMZI) is used to design a new model for an all-optical NOT gate. The nonlinear arm of the NMZI is considered to be made of a slotted-PhC waveguide, where the slot is filled with silicon nanocrystal ( S i N C / S i O 2 ) material. The high nonlinearity of the S i N C / S i O 2 and low group velocity of the PhC make it possible to attain a significant phase shift in low-power high-frequency pulses traveling through the nonlinear arm. A control wave is utilized to increase the phase shift by the cross-phase modulation phenomenon. A complete study on the phase variation is performed by varying various parameters such as powers and pulse widths of the probe and control signal. The study is used to determine the length of the nonlinear arm to calculate the transfer characteristic of the device. The transfer characteristic shows a successful inversion operation in the power range of 28–60 mW for a pulse width of 3 ps. The overall dimension of the device is found as ≈ 112 × 7 µ m 2 . Tolerances of the device performance under fabrication imperfections are analyzed by allowing random variations in the positions and the radii of the holes. This study reveals that the inversion characteristic is sustained, even for the significant fabrication imperfections.

Robust control of a not gate by composite pulses

We present a general procedure to implement a NOT gate by composite pulses robust against both offset uncertainties and control field variations. We define different degrees of robustness in this two-parameter space, namely along one, two or all directions. We show that the phases of the composite pulse satisfy a nonlinear system, and can be computed analytically or numerically.

Speech Encryption Algorithm Based on Nonorthogonal Quantum State with Hyperchaotic Keystreams

With the advancement in modern computational technologies like cloud computing, there has been tremendous growth in the field of data processing and encryption technologies. In this contest there is an increasing demand for successful storage of the data in the encrypted domain to avoid the possibility of data breach in shared networks. In this paper, a novel approach for speech encryption algorithm based on quantum chaotic system is designed. In the proposed method, classical bits of the speech samples are initially encoded in nonorthogonal quantum state by the secret polarizing angle. In the quantum domain, encoded speech samples are subjected to bit-flip operation according to the Controlled–NOT gate followed by Hadamard transform. Complete superposition of the quantum state in both Hadamard and standard basis is achieved through Hadamard transform. Control bits for C-NOT gate as well as Hadamard gate are generated with a modified Lu˙-hyperchaotic system. Secret nonorthogonal rotation angles and initial conditions of the hyperchaotic system are the keys used to ensure the security of the proposed algorithm. The computational complexity of the proposed algorithm has been analysed both in quantum domain and classical domain. Numerical simulation carried out based on the above principle showed that the proposed speech encryption algorithm has wider keyspace, higher key sensitivity and robust against various differential and statistical cryptographic attacks.

Efficient Lattice CP-ABE AC Scheme Supporting Reduced-OBDD Structure for CCN/NDN

In line with the proposed 5th Generation network, content centric network/named data networking (CCN/NDN) has been offered as one of the promising paradigms to cope with the communication needs of future realistic network communications. CCN/NDN allows network communication based on content names and also allows users to obtain information from any of the nearest intermediary caches on the network. Due to that, the ability of cached content to protect itself is essential since contents can be cached on any node everywhere, and publishers may not have total control over their own published data. The attribute based encryption (ABE) scheme is a preferable approach, identified to enable cached contents to be self-secured since it has a special property of encryption with policies. However, most of the proposed ABE schemes for CCN/NDN suffer from some loopholes. They are not flexible in the expression of access policy, they are inefficient, they are based on bilinear maps with pairings, and they are vulnerable to quantum cryptography algorithms. Hence, we propose the ciphertext policy attribute based encryption access control (CP-ABE AC) scheme from a lightweight ideal lattice based on ring learning with error (R-LWE) problem, and demonstrated its use in practical applications. The proposed scheme is proved to be secure and efficient under the decision ring LWE problem in the selective set model. To achieve an efficient scheme, we used an efficient trapdoor technique and the access tree representation of access structure describing the access policies was modified into a new structure, based on a reduced ordered binary decision diagram (reduce-OBDD). This access structure can support Boolean operations such as AND, NOT, OR, and threshold gates. The final result showed that the proposed scheme was secure and efficient for applications, thereby supporting CCN/NDN as a promising paradigm.

Impact of Technology on CNTFET-Based Circuits Performance

In this paper we present a study of the impact of technology on the CNTFET-based circuits performance. In particular we show the layout of a NOT gate, used as block to build a chain of NOT and a ring oscillator. Then we present the time domain simulations of these circuits in order to see how the parasitic elements could limit the high-speed performances of CNTFETs.

Preparing Dicke States on a Quantum Computer

Exact requirement of controlled NOT (CNOT) and single-qubit gates to implement a quantum algorithm in a given architecture is one of the central problems in this computational paradigm. In this article, we take a tutorial approach in explaining the preparation of Dicke states $(\mathinner {|{D^n_k}\rangle })$ using concise realizations of partially defined unitary transformations. We show how to efficiently implement the state-of-the-art deterministic Dicke state preparation circuits and in turn optimize them in terms of CNOT and single-qubit gate counts. We explain theoretical ideas in reducing the gate counts and observe how these improvements are reflected in actual implementation of the circuits. To emphasize the advantages, we describe the circuit for preparing $\mathinner {|{D^4_2}\rangle }$ on the “ibmqx2” machine of the IBM quantum experience (QX) service. Our approach shows that the error induced due to noise in the system is lesser in comparison to the existing works. We conclude by describing the CNOT map of the generic $\mathinner {|{D^n_k}\rangle }$ preparation circuit and analyze different ways of distributing the CNOT gates in the circuit and its effect on the induced error in the Noisy Intermediate Scale Quantum environment.

A bifunctional probe based on naphthalene derivative for absorbance-ratiometic detection of Ag+ and fluorescence “turn-on” sensing of Zn2+ and its practical application in water samples, walnut and living cells

In this work, naphthalene with good biocompatibility was selected, and the probe NBOS was synthesized with 2-Amino-phenol and 2-Amino-benzenethiol. The structure of probe NBOS was confirmed by X-ray Crystallography. Furthermore, the probe showed absorbance-ratiometic sensing for Ag+ over a pH range from 6 to 7.5 and fluorescence “turn on” signal response towards Zn2+ in the pH range of 6–10 in EtOH/H2O (9/1, V/V, pH = 7.4) mixture. The detection limit was obtained to be 4.24 μM for Ag+ and 3.17 nM for Zn2+. Moreover, it could be efficiently recycled by treating Na2EDTA. The sensing mechanism of probe NBOS toward Ag+ and Zn2+ was investigated by FT-IR, HNMR, job’plot and ESI-MS. Typically, the coordination mode of NBOS with Zn2+ was confirmed by DFT calculation. Moreover, probe NBOS was successfully applied in the detection Ag+ and Zn2+ in real water samples. Importantly, probe NBOS could be used to detect Zn2+ in walnut and living cells. Based on the high throughput analysis strategy, absorbance and fluorescence signals of NBOS could be designed as a NOT and OR logic gate controlled by Ag+ (Input 1) and Zn2+ (Input 2).

An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)

The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and inductor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of charge flowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, and hence can be used for non-volatile memory applications. Researchers have been exploring memristors from various perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture for the efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristor aided logic (MAGIC) design style. A Boolean function is first represented as a Binary Decision Diagram (BDD). The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbar architecture with parallel node evaluation where possible. This is the first approach that combines BDD-based synthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-related problems using a slicing architecture. Experimental evaluations on standard benchmark functions show considerable improvement in the solutions.

Power Efficiency of S-Boxes: From a Machine-Learning-Based Tool to a Deterministic Model

Designing cryptographically good and power-efficient $4\times 4$ S-boxes is a challenging problem in the era of lightweight cryptography. Although the optimal cryptographic properties are easy to determine, verifying the power efficiency of an S-box is nontrivial. The conventional approach of determining the power consumption using commercially available CAD tools is highly time-consuming, which becomes formidable while dealing with a large pool of S-boxes. This mandates the development of automation that should quickly characterize the power efficiency from the Boolean function representation of an S-box. In this paper, we present a supervised machine-learning-assisted automated framework to resolve the problem for $4\times 4$ S-boxes, which turns out to be 14 times faster than the traditional approach. The key idea is to extrapolate the knowledge of literal counts, AND–OR–NOT gate counts in the sum-of-products (SOP) form of the underlying Boolean functions to predict the dynamic power efficiency. We demonstrate the effectiveness of our framework by reporting on a set of power-efficient (involutive) optimal S-boxes from a large set of S-boxes. We also develop a deterministic model using results obtained from supervised learning to predict the dynamic power of an S-box that can be used in an evolutionary algorithm to generate cryptographically good and low-power S-boxes.