Normally-off Junction Field-effect Transistor Research Articles

Design of a normally-off diamond JFET for high power integrated applications

Normally-on (depletion mode) and normally-off (enhancement mode) diamond Junction Field Effect Transistors (JFETs) have been analyzed by means of a commercially available TCAD software. First, the parameters used for describing the incomplete ionization, avalanche, and mobility models in diamond have been discussed and assessed against the state-of-the-art. The on- and off-state electrical characteristics of diamond JFETs have been simulated with the suggested parameter values and matched with a set of available experimental data. Secondly, an optimization technique which can improve the performance of an enhancement mode diamond JFET that operates in the unipolar conduction regime has been proposed. This method takes into account the unique properties and limitations of diamond and highlights the main issues that can arise from the design of a normally-off diamond JFET. In particular, the crucial effect of the high temperature on the performance of the normally-off JFET has been investigated. The adopted technique is mainly based on a design of TCAD experiments and no mathematical algorithms have been developed for the calculation of the optimized set of parameters.

Efficiency comparison between Si and SiC‐based implementations in a high gain DC–DC boost converter

An efficiency comparison between a boost converter implemented with silicon (Si) devices and the same converter implemented in the other three cases, that is, employing two combinations of silicon carbide (SiC) devices and a mixture of Si and SiC elements is presented. The converter has been designed for high-voltage low-power applications required by light-emitting diode (LED) lighting. The comparison is performed on an equal basis and discusses the influence on the converter efficiency of the semiconductor power devices and the passive components. The experiments are carried out in a single-stage boost converter prototype delivering a maximum output voltage of 1200 V when supplied by a 12 V battery. The measurements show that the highest efficiency is obtained when the power transistor is implemented by a normally-off junction field-effect transistor and the diode by a SiC Schottky device with a small parasitic capacitance. The implementation with the highest efficiency has been selected for supplying a light spot of 320 LEDs in series, which results in an output voltage of 956 V and an output power of 20.6 W.

High Temperature Performance of Normally-off SiC JFET's Compared to Competing Approaches

Normally-off Silicon Carbide (SiC) power Junction Field Effect Transistors (JFETs) were compared with competing power transistor technology at temperatures from 25 °C to 150 °C as limited by the packaging. Switching energies were measured from 1200 V, 125 mΩ and 50 mΩ (room temperature) rated SiC power JFETs and compared with 900 V silicon (Si) super-junction Metal Oxide Semiconductors (MOSFETs) and 1200 V Si Insulated Gate Bipolar Transistors (IGBTs). For both comparisons, measured performance for the SiC power JFET was advantageous at all temperatures when switching at 50 kHz, including a total switching energy (ESW) of 97 μJ for the SiC JFET, compared with 158 μJ for the Si super-junction MOSFET, and 550 μJ for the Si IGBT at 25 °C. At 150°C, the ESW was 138 μJ for the SiC power JFET, 413 μJ for the Si super-junction MOSFET, and 1020 μJ for the Si IGBT. Increasing the die size of the 1200 V, normally-off SiC JFET by 2.25 resulted in an measured increase in switching energy of 2.7 and 2.37 at 25 °C and 150 °C, respectively, a quasi-linear relationship. Higher power preview products of the SiC normally-off JFET technology were also examined including a 1200 V, 25 mΩ (room-temperature rating) power JFET characterized up to 250 °C, and a module capable of 1200 V, 120 A DC performance at 25 °C.

Growth Mechanism and 2D Aluminum Dopant Distribution of Embedded Trench 4H-SiC Region

The migration enhanced embedded epitaxy (ME3) mechanism and 2D dopant distribution of the embedded trench region is investigated with the aim to realize the all-epitaxial, normally-off junction field effect transistor (JFET). We found that the embedded growth consists of two main components. First one is the direct supply without gas scattering and the other one is the surface migration supply via the trench opening edge, which dominate the ME3 process. An inhomogeneous 2D distribution of Aluminum (Al) concentration was revealed for the first time in the 4H-SiC embedded trench regions by the combined analysis of secondary ion mass spectrometry (SIMS) and scanning spreading resistance microscopy (SSRM) results. The maximum variation of Al concentration in the trench is estimated to be about 4-times, which suggests that the Al concentration is highest for the (0001) plane and lowest for the trench corner (1-10x) plane. Al concentration in the (1-100) plane, which determines the JFET p-gate doping level is 1.5-times lower than (0001) plane for trench region fabricated on Si-face wafers.

Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME 3) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance ( R onS) in the range of 5–10 mΩ cm 2 (1200 V class). A relative high T −2.6 dependence of R onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage ( V th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.