Normalized Min-sum Algorithm Research Articles

An Integrated Orthogonal Frequency-Division Multiplexing Chirp Waveform Processing Method for Joint Radar and Communication Based on Low-Density Parity-Check Coding and Channel Estimation

With the advancement of information technology construction, the integration of radar and communication represents a crucial technological evolution. Driven by the research boom of integrated sensing and communications (ISACs), some scholars have proposed utilizing orthogonal frequency-division multiplexing (OFDM) to separately modulate radar and communication signals. However, the OFDM symbols in this paper incorporate a cyclic prefix (CP) and a virtual carrier (VC) instead of zero padding (ZP). This approach mitigates out-of-band power caused by ZP, in addition to reducing adjacent channel interference (ACI). In addition, we introduce low-density parity-check (LDPC) and use an improved normalized min-sum algorithm (NMSA) in decoding. The enhanced decoding efficiency and minimized system errors render the proposed waveform more suitable for complex environments. In terms of signal processing methods, this paper continues to use radar signals as a priori information to participate in channel estimation. Further, we consider the symbol timing offset (STO) and carrier frequency offset (CFO) issues. In order to obtain more reliable data, we use the minimum mean-square error (MMSE) estimation based on the discrete Fourier transform (DFT) to evaluate the channel. Simulation experiments verify that the system we propose not only realizes the transmission and detection functions but also improves the performance index of the integrated signal, such as the bit error rate (BER) of 7 × 10−5, the peak side lobe ratio (PSLR) of −13.81 dB, and the integrated side lobe ratio (ISLR) of −8.98 dB at a signal-to-noise ratio (SNR) of 10 dB.

New low-density-parity-check decoding approach based on the hard and soft decisions algorithms

<span lang="EN-US">It is proved that hard decision algorithms are more appropriate than a soft decision for low-density parity-check (LDPC) decoding since they are less complex at the decoding level. On the other hand, it is notable that the soft decision algorithm outperforms the hard decision one in terms of the bit error rate (BER) gap. In order to minimize the BER and the gap between these two families of LDPC codes, a new LDPC decoding algorithm is suggested in this paper, which is based on both the normalized min-sum (NMS) and modified-weighted bit-flipping (MWBF). The proposed algorithm is named normalized min sum- modified weighted bit flipping (NMSMWBF). The MWBF is executed after the NMS algorithm. The simulations show that our algorithm outperforms the NMS in terms of BER at 10-8 over the additive white gaussian noise (AWGN) channel by 0.25 dB. Furthermore, the proposed NMSMWBF and the NMS are both at the same level of decoding difficulty.</span>

Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications

This article presents a high throughput and low routing complexity multiframe pipelined low-density parity check (LDPC) decoder design based on a novel pseudo marginalized min-sum (PMMS) message passing approach. The proposed PMMS approach reduces the required number of interconnections in the routing network allowing the design to be implemented with reduced hardware complexity, low power consumption and high throughput capability while supporting multiple coding rates with short and long codewords as defined in many application standards. Implementation results for IEEE802.11ad/ay standards show that the proposed design satisfies a target bit error rate (BER) requirement of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \times 10^{-7}$ </tex-math></inline-formula> with 64 quadrature amp mod (QAM) targeting high throughput applications. Furthermore, the proposed design is able to achieve a throughput of 62 and 101.8 Gb/s with two pipelining stages under 28-nm CMOS and 16-nm FinFET CMOS process, respectively. As compared to the existing NMS algorithm, the proposed design based on the PMMS approach reduces the number of wires in the routing network by 45.5%, and the wirelength of the overall decoder by 17%. The area and power consumption are also reduced by 9.4% and 12%, respectively, as compared to the conventional normalized min-sum (NMS) algorithm.

Improved Layered Normalized Min-Sum Algorithm for 5G NR LDPC

Layered Normalised Min-Sum algorithm is a widely used message passing algorithm for decoding Low Density Parity Check codes. The decoding performance heavily depends on the normalisation factor. Firstly, we leverage the bit structure present in 5G transport blocks to develop an improved decoding algorithm for 5G. Secondly, we determine the optimal normalisation factors of the proposed algorithm using a Deep Neural Network. Performance evaluations show an improvement of 0.3-1.9 dB, with no extra cost on multiplier resources on hardware. Hence, the proposed method is highly attractive for practical 5G decoder implementations.

A Code Rate-Compatible High-Throughput Hardware Implementation Scheme for QKD Information Reconciliation

For high-speed quantum key distribution (QKD) post processing, information reconciliation is the most computational step, which usually acts as the system speed bottleneck. Reconciliation efficiency and operation throughput are the two most important performance parameters, but they are often compromised to each other in actual realization due to the available hardware resources. Another characteristic of the information reconciliation is that its channel is time-varying, and in order to guarantee high efficiency, some rate-compatible error correction scheme should be adopted. To cope with the above problems, this paper proposes a rate-compatible high-efficiency reconciliation algorithm based on quasi-cyclic (QC) low-density parity-check (LDPC) codes and puncturing algorithms. On the other hand, in order to obtain high throughput while maintaining low implementation complexity, the normalized min-sum algorithm (NMSA) is realized and optimized by using the fast prototyping tool of high-level synthesis (HLS). The proposed information reconciliation module was implemented on the Xilinx Zynq Ultrascale+ ZCU102 development board. Experimental results show that the maximum throughput rate of the implemented reconciliation module in this paper can reach 136 Mbps, while the efficiency factor is kept lower than 1.32 across the error rate range of 1.7%∼10.6% under the remaining frame error rate level of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> . The comprehensive good performance obtained by our design can strongly support the development of modern high-speed QKD systems.

A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash

For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve an attractive tradeoff between implementation complexity and decoding performance. In this article, a novel low-bit-width decoding scheme is introduced. In this scheme, the quasi-cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower uncorrectable bit error rate (UBER) with a negligible increase in computational complexity, especially with low-precision input log-likelihood ratio (LLR).

FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

Min-Sum Algorithm Using Multi-Edge-Type Normalized Scheme for ATSC 3.0 LDPC Decoders

To offer commercial LDPC decoders with better performance, in this paper, multi-edge-type (MET) normalized scheme is proposed to improve the performance of traditional min-sum algorithm (MSA) and its modified versions. With respect to sum-product algorithm (SPA), we firstly analyze and find out that the degradations of convergence in different edge types are distinct in MSA theoretically. To compensate the different degradations above, proposed MET-normalized scheme is used in normalized min-sum algorithm (MET-NMSA). In addition, MET-based density evolution (MET-DE) is also presented to search optimized MET-scaling factors for MET-NMSA. To further verify the validity of MET-normalized scheme, Advanced Television Systems Committee (ATSC) 3.0 LDPC codes are used to evaluate MET-NMSA in comparison with the conventional algorithms, i.e., normalized min-sum algorithm (NMSA), offset min-sum algorithm (OMSA) and variable-scaling normalized min-sum algorithm (VS-NMSA). Extensive simulation results show that MET-NMSA for ATSC 3.0 LDPC decoders has at most 1.53dB, 0.21dB and 0.35dB gain over NMSA, OMSA and VS-NMSA respectively when frame error rate (FER) is at 10-4 level over additive white Gaussian noise (AWGN) channels using QPSK modulation.

A Low Complexity Decoding Scheme for Raptor-Like LDPC Codes

Recently, a new structure of low density parity check (LDPC) code named raptor-like LDPC code has attracted much attention. It has better performance at low code rate. In this paper, a novel decoding scheme for raptor-like LDPC code is proposed. First, the Gaussian approximation density evolution (GADE) algorithm is used to track and analyze the message transmission during the decoding process. It is found that certain log likelihood ratio (LLR) messages can be approximated by “zero” setting in the early iteration of raptor-like LDPC decoding. In other words, some column and row operations could be eliminated without compromise the performance. Next, we propose a new decoding scheme, which can skip unnecessary column and row operations. In comparison with the traditional belief propagation (BP)-based LDPC decoding scheme, the proposed scheme can reduce the decoding complexity. Additionally, a new algorithm is developed to facilitate the selection of the early iteration number. With this novel design, the proposed decoding scheme performs almost the same as the traditional BP-based scheme. To proof the concept, the raptor-like LDPC codes in the ATSC3.0 digital TV system are used to evaluate the proposed scheme, in comparison with the traditional BP-based schemes, i.e., sum-product algorithm (SPA), offset min-sum algorithm (OMSA), and normalized min-sum algorithm (NMSA). The simulation results confirm that the proposed scheme can reduce the decoding complexity without sacrifice in performance for all SPA, OMSA, and NMSA methods. About 10% complexity reduction can be achieved. This will reduce the buttery consumption for Internet of Things (IoT) and handheld devices.

Implementation of encoder and decoder for LDPC codes based on FPGA

In this paper, we report an encoding and decoding method for irregular-quasic-cyclic low-density parity-check (IR-QC-LDPC) codes with multi rates. The algorithm is applicable to parity-check matrices which have dual-diagonal parity structure. The decoding adopts normalized min-sum algorithm(NMSA). The whole verification of encoding and decoding algorithm are simulated with MATLAB, if initial bit error ratio is 6% , the code rate of 2/3 is selected, and if the initial bit error ratio is 1.04%, the code rate of 5/6 is selected. We migrate the algorithm from MATLAB to Field Program Gate Array(FPGA) and implement this algorithm based on FPGA. Based on FPGA the throughput of encoding is 183.36Mbps while the average decoding throughput is 27.85Mbps with the initial bit error ratio is 6%.

An Alternative Approach Obtaining a Normalization Factor in Normalized Min‐Sum Algorithm for Low‐Density Parity‐Check Code

The min‐sum algorithm (MSA) for decoding Low‐Density Parity‐Check (LDPC) code is an approximation algorithm that can greatly reduce the computational complexity of the belief propagation algorithm (BPA). To reduce the error between MSA and BPA, an improved MSA such as normalized min‐sum algorithm (NMSA) that uses the normalization factor when updating the check node is used in many LDPC decoders. When obtaining an optimal normalization factor, density evolution (DE) is usually used. However, not only does the DE method require a large number of calculations, it may not be optimal for obtaining a normalization factor due to the theoretical assumptions that need to be satisfied. This paper proposes a new method obtaining a normalization factor for NMSA. We first examine the relationship between the minimum value of variable node messages’ magnitudes and the magnitudes of check node outputs of BPA using the check node message distribution (CMD) chart. And then, we find a normalization factor that minimizes the error between the magnitudes of check node output of NMSA and BPA. We use the least square method (LSM) to minimize the error. Simulation on ATSC 3.0 LDPC codes demonstrates that the normalization factor obtained by this proposed method shows better decoding performance than the normalization factor obtained by DE.

Offset and Normalized Min-Sum Algorithms for ATSC 3.0 LDPC Decoder

Offset min-sum algorithm (OMSA) and normalized min-sum algorithm (NMSA) are widely used in commercial LDPC decoders due to low complexity and reasonable performance. In this paper, we provide optimized offset and scaling values for those LDPC decoders based on Advanced Television Systems Committee (ATSC) 3.0 LDPC codes. Furthermore, according to extensive computer simulations, it is shown that the performance of the OMSA and NMSA with the obtained values is close to that of sum-product algorithm, even though the NMSA-based decoder may show a serious error floor due to a channel mismatch effect. Consequently, we recommend that the ATSC 3.0 transmitters use a concatenation of BCH outer code and LDPC inner code as channel coding, considering the use of NMSA for LDPC decoder in ATSC 3.0 receivers.

An Efficient Combined Bit-Flipping and Stochastic LDPC Decoder Using Improved Probability Tracers

This paper presents an efficient combined bit-flipping (BF) and stochastic low-density parity-check decoder, where a BF decoder is used to achieve a reduction in decoding cycles. A node-wise probability tracer is adopted at each variable node (VN) in order to achieve a BER performance comparable to the normalized min-sum algorithm, where check-to-variable (C2V) messages are used as inputs, rather than the variable-to-check (V2C) messages adopted in previous stochastic decoders. The complexity of the VN units is greatly reduced by sharing common units used in the generation of V2C messages together with a probability tracer. The C2V-based probability tracer enables the design of a decoder that provides a short critical path. The proposed methods are demonstrated by designing a (2048, 1723) decoder that is implemented in a 90 nm process. A total of 1460 K logic gates are integrated in a decoder that has an area of 4.12 $\mbox{mm}^2$ and achieves a coded throughput of 39.3 Gb/s at a clock frequency of 749 MHz. To the best of the authors’ knowledge, the proposed decoder achieves the best normalized throughput-to-area ratio among the stochastic decoders reported in the open literatures.

Dynamic Weighted Bit-Flipping Decoding Algorithms for LDPC Codes

Bit-flipping (BF) decoding of low-density parity-check codes is of low complexity but gives inferior performance in general. To improve performance and provide new BF decoder options for complexity-performance tradeoffs, we propose new designs for the flipping function (FF), the flipped bit selection (FBS) rule and the checksum weight updating schedule. The new FF adjusts the checksum weights in every iteration while our FBS rules take more information into account. These two modifications represent efforts to track more closely the evolutions of both check and variable nodes' reliabilities. Two selective update schedules are proposed to offer more performance and complexity tradeoffs. The combinations of the new FBS rule and known FFs result in new BF decoders with improved performance and a modest complexity increase. On the other hand, combining the new FF and FBS rule gives a new decoder with performance comparable to that of the normalized min-sum algorithm while if we use a much simpler FBS rule instead, the decoder suffers little performance loss with reduced complexity. We also present a simple decision-theoretical argument to justify the new checksum weight formula and a time-expanded factor graph model to explain the proposed selective weight-updating schedules.

Design of a High-Throughput QC-LDPC Decoder With TDMP Scheduling

Low-density parity-check (LDPC) codes with turbodecoding message-passing (TDMP) scheduling can obtain good performance and high convergence rates. In addition, the min- sum (MS) algorithm can reduce the complexity. The hybrid normalized MS algorithm with TDMP scheduling is presented to achieve good performance and to lower the complexity. For a quasi-cyclic LDPC (QC-LDPC) code with a long code length, parallel degree optimization and an offset iterative sequence rule are proposed. With the proposed techniques, the data correlation problem and memory access conflicts during TDMP scheduling can be resolved so that the iteration can smoothly proceed through the reasonable division of each block row. Fabricated in the 90-nm 1-Poly 9-Metal (1P9M) CMOS process, a multimode 96000-bit irregular QC-LDPC decoder is implemented. It attains throughputs of 1.7-3.0 Gb/s and dissipates an average power of 502 mW at an operation frequency of 100 MHz and at 10 iterations. The decoder chip area is 13.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , with a core area of 9.73 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder

In this paper, a power- and area-efficient, multirate, Quasi-cyclic, low-density, parity-check decoder is proposed. The proposed decoder design is based on a simplified adaptive normalized min-sum algorithm. The proposed algorithm effectively utilizes two correction factors for check-node and variable-node update processes. This corrects the channel errors at relatively low signal-to-noise ratio. In order to reduce the finite word length effects, a six-bit nonuniform quantization with the overlapped message passing scheme is used. In addition, an improved early termination scheme is also used to reduce the total number of decoding iterations. This reduces the overall power consumption of the decoder. The simulations have been carried out using Xilinx ISE 14.1 and implemented on Virtex 5 FPGA. The proposed decoder is synthesized using CADENCE with UMC 130 nm technology. With a core area of 1.16 mm$$^{2}$$2, the proposed decoder achieves a maximum throughput of 3.4 Gb/s for 15 decoding iterations with a power dissipation of 114.3 mW.

Variable LLR Scaling in Min-Sum Decoding for Irregular LDPC Codes

Min-sum decoding is a low-complexity alternative to the so-called belief propagation and consists in simplification of the nonlinear operation on the log likelihood ratios (LLRs) in the check nodes. The resulting suboptimality may be tempered via appropriate scaling of the LLRs, e.g., the fixed optimal scaling in the normalized min-sum algorithm, and variable scaling algorithms gradually appearing in the literature. However, up to now, none of the papers studied variable scaling both as per iteration and as per different check node degree, due to the prohibitive complexity of multioptimization over space of too many parameters. In this paper, we propose a generalized mutual information (GMI) of LLRs as the criterion to search for the scaling factors for different check node degrees in every iteration in a 1-D thus low-complexity manner. This approach is first analyzed via density evolution, and in addition can be extended to practical LLRs based formulas via Monte Carlo tools to cope with the mismatch issue. Bit error rate simulation results on two low-density parity-check codes show that our proposed GMI metrics have a noticeable gain over the variable scaling schemes that appeared in the literature.

HSS 기반 초고속 LDPC 복호를 위한 구조

본 논문은 위성방송 전송 규격인 DVB-S2의 기반 채널 부호로 사용되는 LDPC를 고속 복호를 위해 HSS(Horizontal Shuffle Scheduling) 방식을 기반으로 고속 복호기 구조를 연구하였다. 첫째로 HSS방식에서 발생하는 메모리 충돌을 극복하는 방식을 제시한다. 둘째로 고속 복호를 위해 LUT(Look Up Table)을 이용하는 Sum-Product 알로리즘 대신 min값에서 scaling factor를 곱하는 Normalized Min-Sum 알고리즘을 사용하였으며, 성능 향상을 위해 check node에서 bit node로 입력되는 값의 부호를 확인하여 신뢰성 없는 값을 삭제하는 Self-Correct 방식을 제시하여 sum-product 방식에서 발생하는 bottle neck 현상을 하였다. 마지막으로 고속화를 위한 효율적인 메모리 구조를 제안한다. This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc<TEX>${\rightarrow}$</TEX>v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'<TEX>${\rightarrow}$</TEX>c and the sign of the previous incoming messages Moldv'<TEX>${\rightarrow}$</TEX>c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes

The quasi-cyclic low-density parity-check (QC-LDPC) codes are widely applied in digital broadcast and communication systems. However, the decoders are still difficult to be put into practice due to their large area and high power, especially in the wireless mobile devices. This paper presents an improved all-purpose multirate iterative decoder architecture for QC-LDPC codes, which can largely reduce their area and power. The architecture implements the normalized min-sum algorithm, rearranges the original two-phase message-passing flow, and adopts an efficient quantization method for the second minimum absolute values, an optimized storing scheme for the position indexes and signs, and an elaborate clock gating technique for substantive memories and registers. It is also configurable for any regular and irregular QC-LDPC codes, and can be easily tuned up to different code rates and code word lengths. The chip is fabricated in an SMIC 0.18- six-metal-layer standard CMOS technology. It attains a throughput of 104.5 Mb/s, and dissipates an average power of 486 mW at 125 MHz, and 15 decoding iterations. The core area is only 9.76 mm2. The chip has been applied into the China digital terrestrial/television multimedia broadcasting system.

A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue

In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13µm standard CMOS process, the LDPC decoder has an area of 12.51mm2. The required operating frequency to meet the throughput requirement of 135Mbps with maximum iteration number of 30 is 105MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.