Normalized Error Distance Research Articles

Design of floating point multiplier using approximate hybrid Radix-4/ Radix-8 booth encoder for image analysis

This paper presents a novel power efficient Hybrid floating point multiplier (HFPM) with approximate hybrid radix-4/radix-8 booth encoder. This approach efficiently increases the speed of operation and optimises hardware. Compared to existing HFPMs, the proposed HFPM utilises a novel hybrid radix-4/radix-8 booth encoder. The hybrid architecture reduces the computations by an average of k/3 for a k-bit 2’s complement representation by reducing the number of partial products. In addition, to achieve an area-efficient and power-efficient design, approximate computational units are added to the radix-8 booth encoder in the hybrid architecture with a slight reduction in accuracy. The efficiency of the approximate architecture is measured in scales of Error Rate (ER) and Normalized Error Distance (NED). The proposed design is implemented on Kintex 7 FPGA and realized on 45nm ASIC platforms. The experimental study shows that the proposed multiplier has utilised hardware (831 slice LUT, 828 LUT as logic) and consumed 6110 μm2 of area and 83 μW of power which is less as compared to existing floating point multipliers. The experimental results in terms of average Structural Similarity Index Measure (SSIM) is 0.98 which is better than the existing floating point multipliers are compared.

Efficient and low-cost approximate multipliers for image processing applications

The image processing can be implemented in an error-tolerant mode with acceptable accuracy. In digital image processing, the adders and multipliers are the most important components. In this paper, two approximate multipliers based on an approximate 4:2 compressor and two 4-bit full adders with minimizing computational costs are proposed. The first and second proposed approximate multipliers are designed by using the proposed imprecise 4-bit full adders and 4:2 compressor, respectively. In the structure of the proposed multipliers, we have adders for the addition of two multiple-bit numbers. In the adder structure, the full adders are designed based on two modified half adders and one NAND gate. The proposed approximate 4:2 compressor and two approximate 4-bit full adders are compared from hardware and accuracy point of view such as gate count, area-delay product (ADP), error rate (ER), mean error distance (MED), mean relative error distance (MRED), and normalized error distance (NED). The efficacy of proposed multipliers in image processing applications such as image multiplication is evaluated using MATLAB. The results show the proposed approximate multipliers are comparable in terms of area, delay, and mean structural similarity index metric (MSSIM) parameter with other works.

Eye Recognition by YOLO for Inner Canthus Temperature Detection in the Elderly Using a Transfer Learning Approach.

Early detection of physical frailty and infectious diseases in seniors is important to avoid any fatal drawback and promptly provide them with the necessary healthcare. One of the major symptoms of viral infections is elevated body temperature. In this work, preparation and implementation of multi-age thermal faces dataset is done to train different "You Only Look Once" (YOLO) object detection models (YOLOv5,6 and 7) for eye detection. Eye detection allows scanning for the most accurate temperature in the face, which is the inner canthus temperature. An approach using an elderly thermal dataset is performed in order to produce an eye detection model specifically for elderly people. An application of transfer learning is applied from a multi-age YOLOv7 model to an elderly YOLOv7 model. The comparison of speed, accuracy, and size between the trained models shows that the YOLOv7 model performed the best (Mean average precision at Intersection over Union of 0.5 (mAP@.5) = 0.996 and Frames per Seconds (FPS) = 150). The bounding box of eyes is scanned for the highest temperature, resulting in a normalized error distance of 0.03. This work presents a fast and reliable temperature detection model generated using non-contact infrared camera and a deep learning approach.

Design and FPGA Implementation of High Throughput and Low Latency Machine Learning based Approximate Multiplier for Image Processing Applications

One of the uses of approximate circuits is machine learning (ML) and with the help of inexact logic minimization as well as through probabilistic pruning, these approximate computing circuits can be implemented. Nowadays, these approximate circuits have been widely explored due to their essential factors such as compact silicon areas well as low power consumption in movable devices. This research work shows how a 4:2 compressor can be designed using inexact logic minimization and thereby reversing a few bits of the output to ensure efficiency as well as accuracy. The average area, propagation delay as well as the average power of the proposed 4:2 compressor is been calculated and are employed in the 8 × 8 and 16x16 Dadda multiplier and truncation and rounding-based scalable approximate multiplier (TOSAM). Using Vivado Design Software Systems in 45nm technology, all the simulations were carried out and the MATLAB tool make use of error analysis to distinguish between precise as well as approximate proposed circuits. This work is mainly concentrated on the design of exact and approximate multipliers and measures the error between them and minimization of this error using the Machine Learning approach and finally validated the results on the Artix-7 FPGA development board of part XCA7CSG324_110t, the partial products which are generated by multipliers are added using 4:2 compressor adder. In the case of digital processing at nano-metric scales, approximate or inexact computing is considered one of the important examples. For computer arithmetic designs, inexact computation plays a significant role, and the new approximate 4:2 compressors are used in a multiplier that is based on TOSAM. These architectures mainly depend on various compression aspects to enable inaccuracy in computing which is described as error rate and is also referred to as normalized error distance which is used to satisfy circuit-based figures of merit, the number of transistors, delay as well as consumption of power. For a Dadda multiplier, four distinct approaches for exploiting the suggested approximation compressors are designed as well as evaluated. The usage of approximate multipliers for image processing, as well as a wide range of simulation results, are presented in this work. When contrasted to an accurate design, the proposed designs achieve a substantial reduction in the number of transistors, power dissipation as well as delay. Furthermore, the presented multiplier models exhibit outstanding image multiplication capabilities in terms of average normalized error distance as well as peak signal-to-noise ratio that is more than 50dB for the analyzed image samples. The proposed ML-based digital system has been developed in Vivado Design Suite and synthesized which is designed using Verilog HDL. Based on obtained results, 17% reduction in power, 21% reduction in latency, and 33% improvement in throughput.

A modified truncation and rounding-based scalable approximate multiplier with minimum error measurement

<p>Multiplication necessitates more hardware resources and processing time. In a scalable method of approximate multiplier, the truncated rounding technique is added to reduce the number of logic gates in partial products with the help of leading one-bit architecture. Truncation and Rounding based Scalable Approximate Multiplier (TOSAM) has few modes of error measurement based upon height (h) and truncated (t) named as (h,t). These multipliers are named as TOSAM(0,2), TOSAM(0,3), TOSAM(1,5), TOSAM(2,6), TOSAM(3,7), TOSAM(4,8), and TOSAM(5,9). Multiplication provides a substantial impact on metrics like power dissipation, speed, size and power consumption. A modified approximate absolute unit is proposed to enhance the performance of the existing approximate multiplier. The existing 16-bit (3,7) error measurement multiplier shows an error measurement value of 0.4 %. The proposed 16-bit multiplier for the same error measurement possesses the error measured value is of 0.01%, mean relative error measured value of 0.3 %, mean absolute relative error measured value of 1.05, normalized error distance measured value of 0.0027, variance of absolute error measured value of 0.52, delay of 1.87 ns, power of 0.23 mW, energy of 0.4 pJ. The proposed multiplier can be applied in image processing. The work is designed in Verilog HDL and simulated in Modelsim, Synthesized in Vivado.</p>

A Weighted Error Distance Metrics (WEDM) for Performance Evaluation on Multiple Change-Point (MCP) Detection in Synthetic Time Series.

Change-point detection (CPD) is to find abrupt changes in time-series data. Various computational algorithms have been developed for CPD applications. To compare the different CPD models, many performance metrics have been introduced to evaluate the algorithms. Each of the previous evaluation methods measures the different aspects of the methods. Based on the existing weighted error distance (WED) method on single change-point (CP) detection, a novel WED metrics (WEDM) was proposed to evaluate the overall performance of a CPD model across not only repetitive tests on single CP detection, but also successive tests on multiple change-point (MCP) detection on synthetic time series under the random slide window (RSW) and fixed slide window (FSW) frameworks. In the proposed WEDM method, a concept of normalized error distance was introduced that allows comparisons of the distance between the estimated change-point (eCP) position and the target change point (tCP) in the synthetic time series. In the successive MCPs detection, the proposed WEDM method first divides the original time-series sample into a series of data segments in terms of the assigned tCPs set and then calculates a normalized error distance (NED) value for each segment. Next, our WEDM presents the frequency and WED distribution of the resultant eCPs from all data segments in the normalized positive-error distance (NPED) and the normalized negative-error distance (NNED) intervals in the same coordinates. Last, the mean WED (MWED) and MWTD (1-MWED) were obtained and then dealt with as important performance evaluation indexes. Based on the synthetic datasets in the Matlab platform, repetitive tests on single CP detection were executed by using different CPD models, including ternary search tree (TST), binary search tree (BST), Kolmogorov–Smirnov (KS) tests, t-tests (T), and singular spectrum analysis (SSA) algorithms. Meanwhile, successive tests on MCPs detection were implemented under the fixed slide window (FSW) and random slide window (RSW) frameworks. These CPD models mentioned above were evaluated in terms of our WED metrics, together with supplementary indexes for evaluating the convergence of different CPD models, including rates of hit, miss, error, and computing time, respectively. The experimental results showed the value of this WEDM method.

Improving the Quality Degradation of Dynamically Configurable Approximate Multipliers via Data Correlation

In the last few years, dynamically configurable approximate multipliers have been explored to tune the energy-quality trade-off in error-tolerant applications at runtime. Typically, the multiplier accuracy is adjusted by adding a constant correction factor equal to the multiplier mean error to the result, which is found offline assuming a predetermined input distribution. This paper describes a simple approach to update the correction term at runtime, thus adapting it to the actual incoming inputs. It takes advantage of the spatial and/or temporal correlation typically shown by input data in error-tolerant applications, such as image and video processing. When applied to a typical case study implemented with a commercial UTBB FDSOI 28 nm technology, the proposed approach shows an energy reduction of up to 34% at iso-quality and a quality improvement of up to +9 dB, −4× and +35% at iso-energy, in terms of peak-to-noise ratio (PSNR), normalized error distance (NED) and structural similarity index metric (SSIM) respectively, compared to the traditional technique based on a constant correction factor.

Low Power Multiplier using Approximate Compressor for Error Tolerant Applications

Approximate or inexact computing has gained a significant amount of attention for error tolerant systems such as signal processing and image processing applications. In this paper, a comprehensive analysis and evaluation of multipliers realized using the existing approximate 4-2 compressors towards achieving low power has been presented. 8-bit Dadda multiplier has been chosen and the power consumption comparison has been performed. The exact multiplier has also been realized to enable the calculation of power savings for the approximate multipliers. An image compression algorithm using approximate multipliers has been implemented to analyze the operability of the approximate multipliers. Accuracy of the approximate multipliers has also been computed by means of Normalized Error Distance (NED) and PSNR. All the circuits are designed using 45nm CMOS process technology and simulations are carried out using Cadence® Virtuoso design tools.

Approximate Sum-of-Products Designs Based on Distributed Arithmetic

Approximate circuits provide high performance and require low power. Sum-of-products (SOP) units are key elements in many digital signal processing applications. In this brief, three approximate SOP (ASOP) models which are based on the distributed arithmetic are proposed. They are designed for different levels of accuracy. First model of ASOP achieves an improvement up to 64% on area and 70% on power, when compared with conventional unit. Other two models provide an improvement of 32% and 48% on area and 54% and 58% on power, respectively, with a reduced error rate compared with the first model. Third model achieves the mean relative error and normalized error distance as low as 0.05% and 0.009%, respectively. Performance of approximate units is evaluated with a noisy image smoothing application, where the proposed models are capable of achieving higher peak signal-to-noise ratio than the existing state-of-the-art techniques. It is shown that the proposed approximate models achieve higher processing accuracy than existing works but with significant improvements in power and performance.

An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic

Nowadays, portable multimedia devices have been widely used in low-power structures. Additionally, using approximate computing and multiple-valued logic (MVL) can lead to lower power consumption. Carbon nanotube field effect transistor (CNTFET), with a determinable threshold voltage, is an appropriate choice for designing MVL circuits. In this study, a new approximate ternary full adder is presented based on CNTFET switching logic with the aim of reducing area and energy consumption. The results obtained by the Synopsys HSPICE simulator with the Stanford 32 nm CNTFET technology show that the average power consumption, delay, and energy consumption of the proposed designs are significantly lower than the other conventional and state-of-the-art CNTFET-based ternary circuits. In addition, the proposed ternary full adder is applied to reduce the steps of a ternary multiplier structure and some important metrics such as normalized error distance and energy-error trade-off are calculated to evaluate the efficiency of the proposed circuits. The layout of the proposed design is also plotted to estimate area consumption. Moreover, the approximate design is used for image processing applications such as image multiplying and image blending and the results are accordingly compared with the exact outputs. Similarly, the evaluated peak signal-to-noise ratio and mean structural similarity index metric indicate that the proposed approximate full adder has a proper accuracy for image processing applications.

CNFET-based approximate ternary adders for energy-efficient image processing applications

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.

Design and Analysis of Approximate Compressors for Multiplication

Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different features of compression, such that imprecision in computation (as measured by the error rate and the so-called normalized error distance) can meet with respect to circuit-based figures of merit of a design (number of transistors, delay and power consumption). Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Dadda multiplier. Extensive simulation results are provided and an application of the approximate multipliers to image processing is presented. The results show that the proposed designs accomplish significant reductions in power dissipation, delay and transistor count compared to an exact design; moreover, two of the proposed multiplier designs provide excellent capabilities for image multiplication with respect to average normalized error distance and peak signal-to-noise ratio (more than 50 dB for the considered image examples).

New Metrics for the Reliability of Approximate and Probabilistic Adders

Addition is a fundamental function in arithmetic operation; several adder designs have been proposed for implementations in inexact computing. These adders show different operational profiles; some of them are approximate in nature while others rely on probabilistic features of nanoscale circuits. However, there has been a lack of appropriate metrics to evaluate the efficacy of various inexact designs. In this paper, new metrics are proposed for evaluating the reliability as well as the power efficiency of approximate and probabilistic adders. Reliability is analyzed using the so-called sequential probability transition matrices (SPTMs). Error distance (ED) is initially defined as the arithmetic distance between an erroneous output and the correct output for a given input. The mean error distance (MED) and normalized error distance (NED) are then proposed as unified figures that consider the averaging effect of multiple inputs and the normalization of multiple-bit adders. It is shown that the MED is an effective metric for measuring the implementation accuracy of a multiple-bit adder and that the NED is a nearly invariant metric independent of the size of an adder. The MED is, therefore, useful in assessing the effectiveness of an approximate or probabilistic adder implementation, while the NED is useful in characterizing the reliability of a specific design. Since inexact adders are often used for saving power, the product of power and NED is further utilized for evaluating the tradeoffs between power consumption and precision. Although illustrated using adders, the proposed metrics are potentially useful in assessing other arithmetic circuit designs for applications of inexact computing.