Normal Basis Multiplier Research Articles

Novel GF($2_m$) Digit-Serial PISO Multipliers for the Self-Dual Gaussian Normal Bases

Security protocols such as Transport Layer Security implement the Elliptic curve digital signature algorithm (ECDSA) over different binary extension fields defined by the National Institute of Standards and Technology (NIST). Specifically, such multiple cipher-suite support is a security recommendation. Binary extension field arithmetic processors are expensive, especially if more than one field is supported. In this context, this article introduces a novel lightweight digit-serial parallel-in-serial-out (DS-PISO) design for versatile multiplication (DS-VPISO) targeting the NIST-like fields in resource constrained embedded systems where the crypto module allocation is limited. The proposed DS-VPISO multiplier offers competitive area (up to 40 percent area savings) compared to existing multiple field multiplier schemes based on results conducted on bit-serial implementations using Intel's Field programmable gate arrays. The article first presents a DS-PISO self-dual Gaussian normal basis multiplication architecture based on the trace mapping. After this, the article extends the new trace based DS-PISO multiplier to construct an architecture for the first versatile DS-PISO multiplication (DS-VPISO) targeting NIST's binary fields. The latter extension to versatile multiplication is based on novel architectures for versatile cyclic shifts and versatile multiplication by normal elements.

Decomposition of symmetric matrix–vector product over GF (2 m )

Toeplitz matrix–vector product (TMVP) decomposition is an important approach for designing and implementing subquadratic multiplier. In this Letter, a symmetric matrix (SM), which is the sum of a symmetric TM and Hankel matrix, is proposed. Applying the symmetry property, 2-way, 3-way and n-way splitting methods of SMVP is presented. On the basis of 2-way splitting method, the recursive formula of SMVP is presented. Using the two cases n = 4 and 8, the SMVP decomposition approach has less space complexity than 2-way TMVP, TMVP block recombination and symmetric TMVP for even-type Gaussian normal basis multiplication.

Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier

Normal basis multiplication over $GF(2^{m})$ is widely used in various applications such as elliptic curve cryptography. As a special class of normal basis with low complexity, Gaussian normal basis (GNB) has received considerable attention recently. In this paper, we propose a novel decomposition algorithm to develop a digit-level (DL) low-complexity systolic structure for GNB multiplication over $GF(2^{m})$ . First, we propose two algorithms separately to achieve a systolic GNB multiplier with low critical path delay and low register complexity. Next, we present the corresponding structure according to the proposed algorithm (combination of previous two proposed algorithms). Compared with the existing systolic DL GNB multipliers (through both the theoretical and application-specific integrated circuit comparison), the proposed multiplier achieves significantly less area-delay product (ADP), e.g., for a systolic structure of digit size of 8 for $GF(2^{409})$ , the proposed structure has 12.3% less ADP compared to the best of the existing designs, for the same digit size.

Gaussian normal basis multiplier over GF(2m) using hybrid subquadratic‐and‐quadratic TMVP approach for elliptic curve cryptography

In recent years, subquadratric‐and‐quadratric Toeplitz matrix–vector product (TMVP) computations are widely used for the implementation of binary field multiplication in elliptic curve cryptography. Pure subquadratric TMVP structure involves significantly less space complexity and long computational delay, while quadratric TMVP structure involves larger space complexity and less computation delay. To optimise the tradeoff between time and space complexities, this study presents a novel hybrid multiplier for Gaussian normal basis (GNB) in GF(2m) which combines subquadratic and quadratic structures. From the theoretical analysis, it is shown that the proposed hybrid multiplier can save ∼18% space complexity and 12% time complexity than the existing GNB multiplier with pure TMVP decomposition.

Half-Matrix Normal Basis Multiplier Over GF( $p^{m}$ )

In this paper, we propose two new algorithms and their hardware implementations for the normal basis multiplication over GF( $p^{m}$ ), where $p \in \{2, 3\}$ . In this case, the proposed multipliers are designed using serial and digit-serial hardware architectures. The normal basis multipliers over GF( $2^{m}$ ) and GF( $3^{m}$ ) are based on two proposed algorithms to compute the multiplication matrices $T_{k}$ in order to speed-up the execution time and to reduce the area resources. It can be seen that the new hardware architecture for the NB multiplier over GF( $2^{m}$ ) has the best characteristics of area complexity presented by Reyhani [16] and time complexity presented by Azarderakhsh and Reyhani [31] . The proposed hardware architectures for the normal basis multipliers over GF(2163), GF(2233), GF(2283),GF(2409), GF(389) and GF(3233) were described in VHDL, and simulated and synthesized using Modelsim and Quartus Prime v16, respectively.

Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields

Two digit-level finite field multipliers in $\mathbb {F}_{2^{m}}$ using redundant representation are presented. Embedding $\mathbb {F}_{2^{m}}$ in cyclotomic field $\mathbb {F}_{2}^{(n)}$ causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem. Considering area-delay product as a measure of evaluation, it has been shown that both the proposed architectures considerably outperform existing digit-level multipliers using the same basis. It is also shown that for a subset of the fields, the proposed multipliers are of higher performance in terms of area-delay complexities among several recently proposed optimal normal basis multipliers. The main characteristics of the postplace&route application specific integrated circuit implementation of the proposed multipliers for three practical digit sizes are also reported.

Efficient and low‐complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems

In this paper, an efficient high-speed architecture of Gaussian normal basis (GNB) multiplierover binary finite field GF(2m) is presented. The structure is constructed by using some regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. For the powers of 2 exponents, the modules are implemented by some simple cyclic shifts in the normal basis representation. As a result, the multiplier has a simple structure with a low critical path delay. The efficiency of the proposed multiplier is examined in terms of area and time complexity based on its implementation on Virtex-4 field programmable gate array family and also its application specific integrated circuit design in 180 nm complementary metal–oxide–semiconductor technology. Comparison results with other structures of the GNB multiplier verify that the proposed architecture has better performance in terms of speed and hardware utilisation.

An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m)

Finite field multiplication is one of the most important operations in the finite field arithmetic and the main and determining building block in terms of overall speed and area in public key cryptosystems. In this work, an efficient and high-speed VLSI implementation of the bit-serial, digit-serial and bit-parallel optimal normal basis multipliers with parallel-input serial-output (PISO) and parallel-input parallel-output (PIPO) structures are presented. Two general multipliers, namely, Massey–Omura (MO) and Reyhani Masoleh–Hassan (RMH) are considered as case study for implementation. These multipliers are constructed by using AND, XOR–AND and XOR tree components. In the MO multiplier, to have strong input signals and have a better implementation, the row of AND gates are implemented by using inverter and NOR components. Also the XOR–AND component in the RMH structure is implemented using a new low-cost structure. The XOR tree in both multipliers consists of a high number of logic stages and many inputs; therefore, to optimally decrease the delay and increase the drive ability of the circuit for different loads, the logical effort method is employed as an efficient method for sizing the transistors. The multipliers are first designed for different load capacitances using different structures and different number of stages. Then using the logical effort method and a new proposed 4-input XOR gate structure, the circuits are modified for acquiring minimum delay. Using 0.18μm CMOS technology, the bit-serial, digit-serial and bit-parallel structures with type-1 and type-2 optimal normal basis are implemented over the finite fields GF(2226) and GF(2233) respectively. The results show that the proposed structures have better delay and area characteristics compared to previous designs.

High-Performance Two-Dimensional Finite Field Multiplication and Exponentiation for Cryptographic Applications

Finite field arithmetic operations have been traditionally used in different applications ranging from error control coding to cryptographic computations. Among these computations are normal basis multiplications and exponentiations which are utilized in efficient applications due to their advantageous characteristics and the fact that squaring (and subsequent powering by two) of elements can be obtained with no hardware complexity. In this paper, we present 2-D decomposition systolic-oriented algorithms to develop systolic structures for digit-level Gaussian normal basis multiplication and exponentiation over $ {GF}({2}^{m})$ . The proposed high-performance architectures are suitable for a number of applications, e.g., architectures for elliptic curve Diffie–Hellman key agreement scheme in cryptography. The results of the benchmark of efficiency, performance, and implementation metrics of such architectures through a 65-nm application-specific integrated circuit platform confirm high-performance structures for the multiplication and exponentiation architectures presented in this paper are suitable for high-speed architectures, including cryptographic applications.

Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications

Normal basis multiplication in finite fields is vastly utilized in different applications, including error control coding and the like due to its advantageous characteristics and the fact that squaring of elements can be obtained without hardware complexity. In this brief, we present decomposition algorithms to develop novel systolic structures for digit-level Gaussian normal basis multiplication over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The proposed architectures are suitable for high-performance applications, which require fast computations in finite fields with high throughputs. We also present the results of our application-specific integrated circuit synthesis using a 65-nm standard-cell library to benchmark the effectiveness of the proposed systolic architectures. The presented architectures for multiplication can result in more efficient and high-performance VLSI systems.

Parallel and High-Speed Computations of Elliptic Curve Cryptography Using Hybrid-Double Multipliers

High-performance and fast implementation of point multiplication is crucial for elliptic curve cryptographic systems. Recently, considerable research has investigated the implementation of point multiplication on different curves over binary extension fields. In this paper, we propose efficient and high speed architectures to implement point multiplication on binary Edwards and generalized Hessian curves. We perform a data-flow analysis and investigate maximum number of parallel multipliers to be employed to reduce the latency of point multiplication on these curves. Then, we modify the addition and doubling formulations and employ a newly proposed digit-level hybrid-double Gaussian normal basis multiplier to remove the data dependencies and hence reduce the latency of point multiplication. To the best of our knowledge, this is the first time that one employs hybrid-double multiplication technique to reduce the computation time of point multiplication. Moreover, we have implemented our proposed architectures for point multiplication on FPGA and obtained the results of timing and area. Our results indicate that the proposed scheme is one step forward to improve the performance of point multiplication on binary Edward and generalized Hessian curves.

Common Subexpression Algorithms for Space-Complexity Reduction of Gaussian Normal Basis Multiplication

The use of normal bases for representing elements in a binary field is attractive in some applications because it is easy to perform squaring operations in hardware. In such cases, the costs of implementing the multiplication operation become a primary concern. We present new algorithms for reducing the space complexity of Gaussian normal basis multipliers over binary fields GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ), where m is odd. Compared with previous results, our approach incurs no additional costs in time complexity, and achieves improvements in space complexity over a wide range of finite fields and digit sizes. For the binary fields specified in the NIST FIPS 186-3 elliptic curve digital signature algorithm standards document, our algorithms reduce by 16% (respectively, 27%) the number of XOR gates needed for the implementation of a digit-level parallel-input parallel-output multiplier over a 163-bit (respectively, 409 bit) binary field.

Reduction of space complexity based on symmetric TMVP

Toeplitz matrix–vector product (TMVP) decomposition is one of the high-precision multiplication algorithms. A symmetric TMVP (STMVP) decomposition is presented and theoretical analysis shows that the space complexity of the proposed STMVP scheme is less compared with the traditional TMVP approach. Gaussian normal basis (GNB) multiplication based on the proposed architecture can be used to reduce the space complexity.

Low-complexity digit-serial systolic Gaussian normal basis multiplier for curve-based cryptosystems

Finite field multiplication over GF(2m) is one of the most important arithmetic operations for curve-based cryptosystems, such as elliptic curve cryptosystems and pairing-based cryptosystems. Gaussian normal basis (GNB) multiplier is very suitable for realizing finite field multiplication in curve-based cryptosystems because GNB multiplier is highly efficient in performing square operations of multiplicative inversion, squaring, and exponentiation operations. Therefore, this study will present a digit-serial GNB multiplier with unidirectional systolic array which is suitable for fault-tolerant design and very large scale integrated circuits implementation. The proposed digit-serial GNB multiplier can save about 22% space complexity and requires almost the same time complexity when compared with the existing similar multipliers.

가우시안 정규기저를 갖는 GF(2n)의 곱셈에 대한 오류 탐지

본 논문에서는 가우시안 정규기저를 갖는 유한체 <TEX>$GF(2^n)$</TEX>의 곱셈기 오류 탐지 방법을 제시한다. 제안하는 오류 탐지 방법은 하드웨어로 단순하게 구성된다. 즉 n-bit 출력 직렬 곱셈기에서는 1 개의 AND gate, n+1 개의 XOR gate, 그리고 1 개의 1-bit register로 구성되며, 병렬 곱셈기의 경우 n 개의 AND gate와 2n-1 개의 XOR gate로 구성된다. 제안하는 방법은 C=AB 연산에 홀수개의 오류가 발생하는 경우 탐지가 된다. In this paper, we proposed an error detection in Gaussian normal basis multiplier over <TEX>$GF(2^n)$</TEX>. It is shown that by using parity prediction, error detection can be very simply constructed in hardware. The hardware overheads are only one AND gate, n+1 XOR gates, and one 1-bit register in serial multipliers, and so n AND gates, 2n-1 XOR gates in parallel multipliers. This method are detect in odd number of bit fault in C = AB.

Low-Complexity Multiplier Architectures for Single and Hybrid-Double Multiplications in Gaussian Normal Bases

The extensive rise in the number of resource constrained wireless devices and the needs for secure communications with the servers imply fast and efficient cryptographic computations for both parties. Efficient hardware implementation of arithmetic operations over finite field using Gaussian normal basis is attractive for public key cryptography as it provides free squarings. In this paper, we first present two low-complexity digit-level multiplier architectures. It is shown that the proposed multipliers outperform the existing Gaussian normal basis (GNB) multiplier structures available in the literature. Then, for the first time, using these two architectures, we propose a new digit-level hybrid multiplier which performs two successive multiplications with the same latency as the one for one multiplication. We have studied the efficiency of the proposed hybrid architecture in terms of area and time delay for different digit sizes. The main advantage of this new hybrid architecture is to speed up exponentiation and point multiplication whenever double-multiplication is required and the traditional schemes fail due to the data dependencies. We have investigated the applicability of the proposed hybrid structure to reduce the latency of exponentiation-based cryptosystems. Our analysis and timing results show that the expected acceleration in double-exponentiation is considerable. Prototypes of the presented low-complexity multiplier architectures and the proposed hybrid architecture are implemented and experimental results are presented.

High-Performance Implementation of Point Multiplication on Koblitz Curves

Fast and high-performance computation of finite-field arithmetic is crucial for elliptic curve cryptography (ECC) over binary extension fields. In this brief, we propose a highly parallel scheme to speed up the point multiplication for high-speed hardware implementation of ECC cryptoprocessor on Koblitz curves. We slightly modify the addition formulation in order to employ four parallel finite-field multipliers in the data flow. This reduces the latency of performing point addition and speeds up the overall point multiplication. To the best of our knowledge, the proposed data flow of point addition has the lowest latency in comparison to the counterparts available in the literature. To make the cryptoprocessor more efficient, we employ a low-complexity and efficient digit-level Gaussian normal basis multiplier to perform lower level finite-field multiplications. Finally, we have implemented our proposed architecture for point multiplication on an Altera Stratix II field-programmable gate array and obtained the results of timing and area.

Palindromic-like representation for Gaussian normal basis multiplier over GF(2 m ) with odd type t

Palindromic representation is generally used to reduce space and time complexities in Gaussian normal basis (GNB) multiplier with even type t. However, palindromic representation is inapplicable for a GNB multiplier with odd type t ($t \geq 2$). This study therefore develops a palindromic-like representation for a GNB multiplier with odd type t. The proposed systolic GNB multiplier with odd type t reduces space and time complexities by as much as 50% compared with conventional GNB multiplier with odd type t without palindromic representation.

Low-complexity Gaussian normal basis multiplier over GF(2 m )

The elliptic curve cryptosystem (ECC) is very attractive for the use in portable devices because of the small key size. The finite field multiplication over GF(2m) is the most important arithmetic for performing the ECC. Portable devices usually have restricted computation power and memory resources. This work will present a simple method for designing a Gaussian normal basis (GNB) multiplier over GF(2m) needing only fewer computation power whereas keeping lower cost. The proposed Gaussian NB multiplier saves ∼57% space complexity as compared with existing GNB multiplier.

Fault-tolerant Gaussian normal basis multiplier over GF(2 m )

Fault-tolerant design of a finite field multiplier is an efficient method for resisting fault-based cryptanalysis in Elliptic curve cryptosystems. A novel fault-tolerant bit-parallel Gaussian normal basis (GNB) multiplier with type-t over GF(2m), which can tolerate multiple module failures at one time, is presented. No hardware modification in the proposed GNB multiplier is required to achieve the fault-tolerant function. Hence, the proposed fault-tolerant GNB multiplier has low hardware cost. The reliability of the proposed fault-tolerant GNB multiplier with type-t increases as t increases. However, the behaviour of existing GNB multipliers with concurrent error correction (CEC) resembles triple modular redundancy (TRM) when t>3. In practice, most of suggested m's by NIST use GNB with type-t>3. The proposed fault-tolerant GNB multiplier is an N-modular redundancy (NMR) system with N=t. Thus, the proposed fault-tolerant GNB multiplier with type-t can tolerate at most t/2-1 failed modules simultaneously, while existing GNB multipliers with CEC only can tolerate one failed module. The proposed GNB multiplier requires less extra space and time complexities than similar multipliers. System reliability of the proposed fault-tolerant GNB multiplier is better than that of similar GNB multipliers.