Normal Basis Multiplier Research Articles

Efficient digit-serial normal basis multipliers over binary extension fields

In this article, two digit-serial architectures for normal basis multipliers over ( GF (2 m )) are presented. These two structures have the same gate count and gate delay. We also consider two special cases of optimal normal bases for the two digit-serial architectures. A straightforward implementation leaves gate redundancy in both of them. An algorithm that can considerably reduce the redundancy is also developed. The proposed architectures are compared with the existing ones in terms of gate and time complexities.

Fast normal basis multiplication using general purpose processors

For cryptographic applications, normal bases have received considerable attention, especially for hardware implementation. We consider fast software algorithms for normal basis multiplication over the extended binary field GF(2/sup m/). We present a vector-level algorithm, which essentially eliminates the bit-wise inner products needed in the conventional approach to the normal basis multiplication. We then present another algorithm, which significantly reduces the dynamic instruction counts. Both algorithms utilize the full width of the data-path of the general purpose processor on which the software is to be executed. We also consider composite fields and present an algorithm, which can provide further speed-ups and an added flexibility toward hardware-software codesign of processors for very large finite fields.

Efficient multiplication beyond optimal normal bases

In cryptographic applications, the use of normal bases to represent elements of the finite field GF(2/sup m/) is quite advantageous, especially for hardware implementation. In this article, we consider an important field operation, namely, multiplication which is used in many cryptographic functions. We present a class of algorithms for normal basis multiplication in GF(2/sup m/). Our proposed multiplication algorithm for composite finite fields requires a significantly lower number of bit level operations and, hence, can reduce the space complexity of cryptographic systems.

Key function of normal basis multipliers in GF (2 n )

A new definition of the key function in GF(2n) is given. Based on this definition, a method to speed up software implementations of the normal basis multiplication is presented. It is also shown that the normal basis with maximum complexity can be used to design low complexity multipliers. In particular, it is shown that the circuit complexity of a type I optimal normal basis multiplier can be further reduced.

Low-complexity bit-parallel canonical and normal basis multipliers for a class of finite fields

We present a new low-complexity bit-parallel canonical basis multiplier for the field GF(2m) generated by an all-one-polynomial. The proposed canonical basis multiplier requires m/sup 2/-1 XOR gates and m/sup 2/ AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier.

A search of minimal key functions for normal basis multipliers

The circuit complexity of a Massey-Omura normal basis multiplier for a finite field GF(2/sup m/) depends on the key function for multiplication. Key functions with minimum complexity, called minimal key functions, are desirable. This paper investigates the complexity of a key function and reports search results of minimal key functions. A table of minimal key functions for m up to 31 is included.

Self-dual bases in $$\mathbb{F}_{q^n } $$

We characterize weakly self-dual bases of the field extension\(\mathbb{F}_{q^n } \) over\(\mathbb{F}_q \), examine the existence of weakly self-dual polynomial bases, and use duality to analyze normal basis multiplication.

A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>