NOR Flash Research Articles

Modeling charge variation during data retention of MLC Flash memories

In this paper, we propose to model charge variation in Multi-Level Cells in NOR Flash memories. We first define a sensitivity-to-temperature factor to determine the number of involved mechanisms. Then, according to previous studies, we can use the Poole–Frenkel (PF) and/or the Fowler–Nordheim (FN) equations to model every charge loss, which we apply to our cells. We succeed in modeling our data retention measurements by superimposing these two phenomena, being, respectively preponderant at the beginning and at the end of the data retention measurements, as shown by the factor of sensitivity-to-temperature. We have then found a relationship between temperatures to evaluate our cells lifetime. We validate that the classical 1/ T Arrhenius law is not the most appropriate and that a T model can be better. We also model a fictive charge gain by using a negative charge front displacement in the tunnel oxide. This study can easily be extended to any floating gate non-volatile memory.

Various Flash Memory Devices of Novel Design

Various novel flash memory devices for both NOR and NAND types are reviewed. In NOR-type flash memory devices, 2-bit/cell devices and their technology trends are addressed. Furthermore, multi-site charge-trapping schemes with more-than-2-bit/cell operation are also studied in the fin SONOS (silicon oxide-nitride oxide semiconductor) flash memory having independent double gates and the stacked vertical-channel NOR flash memory. In the NAND-type flash memory, devices having extended word-lines are investigated. As well as the short-channel effect, fluctuation and process limitation issues are considered for the highly scaled devices. Some future perspectives, including a stacked array, are discussed for high-density NAND flash memories.

A Novel Structure for Beyond-45 nm NOR Flash Technology Featuring Short Channel Effect Immunity and Low Random Telegraph Signal Noise

We proposed a three-dimensional (3D) flash structure named recessed channel array transistor (RCAT), aiming to archive good short channel immunity and lower random telegraph signal (RTS). The results show that RCAT cell can keep a 110 nm effective gate length and consequently a punch-through voltage above 5 V even in 45 nm technology node. In RCAT cell, the RTS Vth variation was reduced from 0.5 to 0.2 V compared with planar cell due to enlarged gate length and lower channel dopant concentration. These advantages of RCAT cell make it a promising structure for the continuous scaling of the NOR flash memories to 45 nm and beyond.

Organic Offset Deposition by Innovative Plasma Technology: Channel Length Modulation for NOR Flash Memories

NOR flash memories typically use a Self Aligned Source (SAS) approach to increase array density and reduce device size. A low resistance source line common to adjacent cells in different bitlines is obtained by etching field oxide and implanting N-type dopant. The thin organic layer left by reactive ion etch (RIE) acts as a spacer during the implantation step, impacting the effective channel length and the source line resistance. Cell parameter variations induced by unpredictable changes of this film cannot be neglected as second order effects for 65nm and subsequent technology nodes. This paper discusses a new plasma technology application focused on this topic: after removing the organic film left by RIE, a tunable offset spacer has been purposely deposited on cell sidewalls and characterized by means of TEM analyses. The corresponding electrical impact on cell properties is reported and discussed.

Future challenges of flash memory technologies

Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45 nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32 nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution.

A Novel Body-Tied Fin Field Effect Transistor Flash Memory Structure with λ-Shaped Floating Gate for Sub 45 nm NOR Flash Memory

A novel body tied (BT) fin field effect transistor (FinFET) flash structure with λ-shaped floating gate was firstly demonstrated for sub 45 nm NOR flash memory. Using this structure, high on cell current and punch-through immunity with a good reliability have been achieved. In this structure, the neighboring cell interference has been effectively reduced, which makes it feasible to increase the coupling ratio of FinFET cells through raising the floating gate height. In addition, the random telegraph signals noise (RTN) and its impact on the threshold voltage (Vth) variation of flash cells have been intensively studied. It was found that RTN Vth variations in the λ-shaped BT-FinFET cells are significantly suppressed thanks to the increased active area and enhanced on current.

Integration of CVD silicon nanocrystals in a 32 Mb NOR flash memory

In this paper, silicon nanocrystals (Si-NCs) fabricated by Chemical Vapor Deposition (CVD) are successfully integrated in a 32Mb ATMEL NOR Flash memory product, processed in a 130nm technology platform. Different Si-NC deposition conditions are explored and the threshold voltage distributions of the arrays are correlated to the Si-NC size/dispersion. Main reliability characteristics, as endurance and data-retention after cycling, are studied. Results obtained on large arrays are related to single cell characteristics. The large set of data measured on arrays clearly demonstrates the robustness of our process and integration scheme.

Cycling Effect on the Random Telegraph Noise Instabilities of nor and nand Flash Arrays

The impact of program/erase (P/E) cycling on the random telegraph noise (RTN) threshold voltage instability of NOR and NAND flash memories is studied in detail. RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations on the cells. Tail height is shown to increase as a function of the stress levels, with a larger relative increase for the NAND case. The slope of the distribution instead remains nearly independent of the number of applied P/E cycles. This reveals that trap generation takes place according to the native trap distribution over the active area and means that the tail slope is a basic RTN parameter, depending on the cell process details for a fixed technology. These results are important for the design of the threshold voltage levels in multilevel nor and NAND technologies.

A New Architecture for High-Density High-Performance SGT nor Flash Memory

In order to overcome the limitation of a conventional NOR flash memory, we propose a new architecture using a surrounding gate transistor (SGT) NOR flash memory to realize both Fowler-Nordheim (FN)-tunneling program and high-speed random access read operation. The SGT NOR flash memory cell has a 3D structure, in which the source, gate and drain are vertically stacked. The gate surrounds a silicon pillar. The source line of a diffusion layer and the metal bit line (BL) are wired to the bottom and the top of the silicon pillar, respectively. The BL and SL are arranged in the same column direction and the gate line is wired in the row direction. This structure enables the same voltage to be simultaneously applied to both the SL and BL of the same column. Therefore, the SGT NOR flash memory cell can be written and erased by the FN-tunneling mechanism. In read operation, the metal common SL is connected with the SL every 16 memory cells to reduce the resistance of the SL. As a result, a read current is improved and a high-speed read operation can be achieved. Furthermore, the SGT NOR flash memory adapts to 50-nm node to obtain a compact cell area of 6.6 and a large read current of 72 muA; the cell area can be reduced by 54% and a read current increase by 227% compared to the conventional NOR flash memory. Owing to high-density and high-speed features, the SGT NOR flash memory is a promising structure for the future high-density and high-performance flash memory.

Organic Offset Deposition by Innovative Plasma Technology: Channel Length Modulation for NOR Flash Memories

not Available.

Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure

A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (Vth) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (Vth, DIBL and SS) by considering device structure and doping profile of the cell.

Two-Bit/Cell NFGM Devices for High-Density NOR Flash Memory

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the V th margin for 2-bit/cell operation by ~2.5 times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the V th margin more than ~1.5V. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better △V th and V th margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ~10 nm below the source/drain junction.

Analysis and test procedures for NOR flash memory defects

Widespread use of non-volatile memories, especially flash memories, in diverse applications such as in mobile computing and system-on-chip is becoming a common place. As a result, testing them for faults and reliability is drawing considerable interest of designers and researchers. One of the most predominant failure modes for which these memories must be tested is called disturb faults. In this paper, we first analyze different defects that are responsible for disturb faults using a 2-dimension device simulator. We determine the impact of various defects on cell performance and develop a methodology based on channel erase technique to detect these defects. Our tests are efficient and can be converted to march tests prevalently used to test memories. We also propose a very low cost design-for-testability approach that can be used to apply the test technique developed in this paper.

The future of phase-change semiconductor memory devices

Phase-change memory (PCM) has recently been under active development by a number of semiconductor manufacturing companies and research laboratories. This development has been accelerated both by the rapidly growing market for nonvolatile memory in cellular phones and other types of portable electronic equipment and by the realization that Flash memory, the currently dominant nonvolatile memory technology, will face serious challenges as it scales in the future to smaller and smaller dimensions. PCM nonvolatile memory technology has shown scaling, speed, and endurance characteristics which could allow it to replace Flash memory in future applications and, perhaps in time, DRAM memory as well. Commercial introduction of PCM memory chips which can replace NOR Flash is anticipated to begin this year. The performance and scaling advantages of PCM are a direct consequence of the memory cell device physics and fundamental properties of the phase-change alloys and these will be reviewed in light of future memory requirements and competition from other emerging memory technologies.

A Hybrid Flash File System Based on NOR and NAND Flash Memories for Embedded Devices

This paper presents a hybrid flash file system (HFFS) based on both NOR flash and NAND flash memory. In a conventional NAND flash-based flash file system, there is a trade-off between life span and durability in the frequent writing of small amounts of data. Because NAND flash supports only a page-level I/O, at least one page is wasted in the synchronous writing of small amounts of data. The wasting of pages reduces the utilization and life span of the NAND flash. To alleviate the utilization problem, some NAND flash-based flash file systems write small amounts of data asynchronously with RAM buffers, though buffering in RAM decreases the durability of the system. Our HFFS eliminates the trade-off between life span and durability. It synchronously stores data as a log in the NOR flash, whenever we append small amounts of data to a file. The merged logs are then flushed to the NAND flash in a page-aligned fashion. The implementation of our HFFS is based on our previous NAND flash-based file system, called CFFS, The experimental results reveal that our HFFS provides a longer life span than a conventional NAND flash-based synchronous flash file system with a similar level of durability.

A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface

This paper describes a 1.8 V, 1 Gb 2 b/cell NOR flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns random access time and a 400 MB/s sustained read throughput via a DDR interface.

The Enabling of an Execute-In-Place Architecture to Reduce the Embedded System Memory Footprint and Boot Time

Success in the embedded world revolves around two key concepts: cost effectiveness and performance. The ability for an operating system to boot quickly combined with speedy application usage at runtime is important to consumer unit adoption. The most common memory sub-system setup in cellular phone architectures today is what is called an eXecute-In-Place architecture. This type of memory subsystem defines the execution of code and data directly from NOR flash memory. An additional memory architecture of choice is called a Store and Download architecture. This is a memory sub-system where the code gets copied to RAM at boot time and executes out of the RAM. This paper explores the addition of a new memory usage model called a Balanced XIP System. By choosing to use a Balanced XIP System you will save battery life while utilizing system resources. This is important in an age where lifestyle is driven by quick data access and electronic device energy longevity. The result is a system that combines a small RAM memory requirement with a performance increase for improved targeted application and boot time execution.

Single Event Effect Characterization of High Density Commercial NAND and NOR Nonvolatile Flash Memories

Heavy ion single-event measurements on a variety of high density commercial NAND and NOR flash memories were reported. Three SEE phenomena were investigated: SEUs, SEFIs, and catastrophic loss of ability to erase and write to the device. Although for all devices under test SEUs and SEFIs were observed, these commercial high densities devices appear to be much less susceptible than typical flash devices that have been tested lately. A new high current phenomenon in the high density NAND flash memories and charge pump failure in the NOR flash memory are discussed.

Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure

We characterized length effect of the spacer-type storage node in 2-bit/cell silicon–oxide–nitride–oxide–silicon (SONOS) flash memory device with recessed channel structure for 50 nm non-volatile memory (NVM) technologies. A proposed memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region. Device which has the charge storage length of 40 nm shown better ΔVth and Vth margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ∼10 nm below the source/drain junction. Especially, in case of given read bias for forward or reverse read, the sensing current was more stable with shorter length of the storage layer.

Design Technology to Lower Resistance of Source Line for SGT NOR Flash Memory

not Available.