NOR Flash Cell Research Articles

Physically-based evaluation of aging contributions in HC/FN-programmed 40 nm NOR Flash technology

In this paper, an in-depth aging assessment for 40nm NOR Flash cells, programmed by Hot Carrier (HC) and erased by Fowler-Nordheim (FN) mechanisms, is performed during Program/Erase (P/E) cycling. Firstly, the difficulty of properly analyzing the overall HC+FN wear out and the importance of evaluating the different cell characteristic drifts are pointed out. Thus, in order to thoroughly explore the cell degradation, ad-hoc experimental setup and test structures are considered. In particular, using customizable gate patterns during P/E operations, the cell endurance is successfully reproduced on equivalent Flash transistors. Taking advantage of these results and of cell dynamics computation within P/E phases, a fine extraction and separation of electrostatic and cell performance decays within the Programming Window (PW) evolution is presented. Then, using this technique, an accurate physical assessment of cell aging characteristic evolutions under different gate ramp patterns is provided. This attitude is shown to give important guidelines for the optimization of Flash cell endurance performance for a certain initial PW. In particular, the erase pattern is demonstrated not to significantly influence the PW drift, whereas, lowering the ramp speed during the program operation, an important increase of Vth in both states is observed and physically explained.

Characterizing Radiation and Stress-Induced Degradation in an Embedded Split-Gate NOR Flash Memory

Radiation and stress-induced degradation are characterized in split-gate NOR flash cells through a set of unique experiments. Radiation and program/erase stress on the bit cells is shown to create both positive and negative traps in the oxide around the floating gate cell. The annealing temperature following radiation determines the rate at which oxide traps are neutralized. To analyze both program/erase and radiation induced damage in greater detail; partial program and erase operations are performed. The implications of this work for both radiation hardness assurance testing and device reliability are discussed.

A Novel High Programming Efficiency and Highly Scalable Flash Memory Cell Based on Tunneling FET (TFET)

A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is proposed and investigated in this paper. Based on the TFET structure, the proposed novel flash memory cell shows high programming efficiency, low power consumption, and good punch-through immunity. Unlike traditional NOR Flash cell which adopts the channel hot carrier (CHE) injection near drain side for programming operation, the TFET flash memory cell utilizes hot electrons injection introduced by band-to-band tunneling near source side for programming, which can achieve 3 orders higher programming efficiency due to greatly alleviated competition between the vertical electric field and lateral electric field. Moreover, the programming leakage current is 2 orders lower due to the high punch-through immunity for TFET structure. The obtained results and theoretical analysis demonstrate that the newly proposed flash cell can be a potential candidate for low power, and high density NOR-type flash applications.

Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure

We characterized length effect of the spacer-type storage node in 2-bit/cell silicon–oxide–nitride–oxide–silicon (SONOS) flash memory device with recessed channel structure for 50 nm non-volatile memory (NVM) technologies. A proposed memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region. Device which has the charge storage length of 40 nm shown better ΔVth and Vth margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ∼10 nm below the source/drain junction. Especially, in case of given read bias for forward or reverse read, the sensing current was more stable with shorter length of the storage layer.

The effect of dimensional scaling on the erase characteristics of NOR flash memory

In this letter, new limitations on the NOR flash cell scaling have been presented. As cell scaling is continued, a parasitic capacitance between floating gate and bitline contact induces a large disturbance to the Fowler-Nordheim tunneling characteristics due to a coupling ratio variation, resulting in a much broader erase threshold distribution. Theoretical analysis including MEDICI simulations confirms the effects of parasitic capacitance on the erase threshold of NOR flash cells.

Introduction to flash memory

This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Impact of floating gate dry etching on erase characteristics in NOR flash memory

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.

Bake induced charge gain in NOR flash cells

Charge gain, caused by localized defects in the tunnel oxide of floating gate devices, is one of the central reliability concerns of flash memory. In this work, we show that charge motion in the poly sidewall spacers of flash cells can also result in substantial charge gain, for nonoptimized processes. Data showing the time, temperature, and field dependencies of this charge gain mechanism are presented. It is shown that the threshold voltage shift caused by charge motion in the poly sidewall spacers follows the simple factorial expression: /spl Delta/V/sub th/=C/spl middot/V/sub fg//spl middot/t/sup /spl alpha///spl middot/e/sup -/spl epsiv/(a)/kT/.