Abstract

In this paper, an in-depth aging assessment for 40nm NOR Flash cells, programmed by Hot Carrier (HC) and erased by Fowler-Nordheim (FN) mechanisms, is performed during Program/Erase (P/E) cycling. Firstly, the difficulty of properly analyzing the overall HC+FN wear out and the importance of evaluating the different cell characteristic drifts are pointed out. Thus, in order to thoroughly explore the cell degradation, ad-hoc experimental setup and test structures are considered. In particular, using customizable gate patterns during P/E operations, the cell endurance is successfully reproduced on equivalent Flash transistors. Taking advantage of these results and of cell dynamics computation within P/E phases, a fine extraction and separation of electrostatic and cell performance decays within the Programming Window (PW) evolution is presented. Then, using this technique, an accurate physical assessment of cell aging characteristic evolutions under different gate ramp patterns is provided. This attitude is shown to give important guidelines for the optimization of Flash cell endurance performance for a certain initial PW. In particular, the erase pattern is demonstrated not to significantly influence the PW drift, whereas, lowering the ramp speed during the program operation, an important increase of Vth in both states is observed and physically explained.

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