Abstract
Flash cell endurance performance is one of the most important index for flash technology, it becomes more and more challenge during the NOR flash cell scaling down. In this paper, it was reported the mechanism analysis and improvement method for NOR Flash cell endurance burn out in the advanced node beyond 65nm. Tunnel oxide, inter poly dielectric(IPD) film, dielectric film between control gate(CG) to active area(AA) have been analyzed through various experiments to explain the mechanism for NOR Flash cell endurance burn out. To be noticed, we found that CG to AA interface defect reduction and optimized chip probing (CP) screen methodology could be extremely good to enhance NOR Flash cell endurance performance.
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