Nonvolatile Random Access Memory Research Articles

Solution-processed black phosphorus nanoflakes for integrating nonvolatile resistive random access memory and the mechanism unveiled

In this study, we demonstrated the integration of black phosphorus (BP) nanoflakes in a resistive random access memory (RRAM) with a facile and complementary metal-oxide-semiconductor-compatible process. The solution-processed BP nanoflakes embedded in polystyrene (PS) as an active layer were sandwiched between aluminum electrodes (Al/BP:PS/Al). The device shows a figure of merit with typical bipolar behavior and forming-free characteristics as well as excellent memory performances such as nonvolatile, low operation voltage (1.75 V) and high ON/OFF ratio (>102) as well as the long retention time (>1500 s). The improved device performances were attributed to the formation of effective trap sites from the hybrid structure of the active layer (BP:PS), especially the BP nanoflakes and the partly oxidized species (PxOy). Moreover, the extrinsic aluminum oxide layer was observed after the device operation. The mechanism of switching behavior was further unveiled through the carrier transport models, which confirms the conductive mechanisms of space-charge-limited current and Ohmic conductance at high resistance state (HRS) and low resistance state, respectively. Additionally, in the high electric field at HRS, the transfer curve was well fitted with the Poole–Frenkel emission model, which could be attributed to the formation of the aluminum oxide layer. Accordingly, both the trapping/de-trapping of carriers and the formation/rupture of conductive filaments were introduced as transport mechanisms in our devices. Although the partial PxOy species on BP were inevitable during the liquid phase exfoliation process, which was regarded as the disadvantages for various applications, it turns to a key point for improving performances in memory devices. The proposed approach to integrating BP nanoflakes in the active layer of the RRAM device could pave the way for next-generation memory devices.

Design of memristor based low power and highly reliable ReRAM cell

A CNFET-based nonvolatile 4CNFET2M resistive RAM (ReRAM) cell is proposed in this paper. In this design, four CNFETs are employed as high-speed, low power and high endurance switches while the two memristors constitute the memory element. In this paper, the proposed 4CNFET2M ReRAM has been compared with the standard 6T SRAM (S6T) cell and the contemporary 2T2M ReRAM cell. The proposed cell shows 1.68 ×/2.14 × shorter read delay (TRA) when compared to S6T/2T2M while exhibiting 4.16 × shorter write delay (TWA) than that of 2T2M @ VDD = 1 V. Moreover, at VDD = 1 V, it displays a 2.32 × narrower spread in TWA than 2T2M as well as 8.0 ×/7.25 × narrower spread in TRA than that of S6T/2T2M. The proposed cell consumes 2.57 × 106 ×/2.70 × lower hold power (HPWR) than that of S6T/2T2M at VDD = 1 V. In addition, it exhibits tolerance to variations in temperature as well as pitch and Vth of memristor. All this is achieved at a 32.44 × penalty in TWA when compared to S6T. The use of CNFET devices, which possess far superior electrical characteristics in comparison to traditional CMOS devices, integrated with memristor technology, paves the way for such major improvements in design metrics of the proposed cell.

Study on the effect of re-deposition induced by ion beam etching on MTJ performances

Magnetic tunnel junction (MTJ) as a key spintronics device can be used for the high-sensitivity magnetic field sensor and high-density non-volatile magnetic random access memory (MRAM). To obtain a high tunneling magnetoresistance (TMR), precise control of the etching process for MTJs is an essential step. In order to investigate the effect of the etching angle on the performance of MTJ devices, a series of MTJ pillars are fabricated by etching with the incidence angle of 10°, 20° and 30°. The prepared samples are characterized by the optical microscopy and SEM, and the R-H curves are also measured and then statistically analyzed. The results reveal that the performance of the MTJ is strongly affected by the IBE process, displaying the uniformity of the pillars edge and MTJ performance will improve as well with the increase of the etching angle. Then, a simplified model based on the re-deposition effect of the etching process is established to explain the experimental phenomena. Furthermore, a newly defined material parameter is introduced in this model and obtained with fitting the experimental results. This proves a valuable way to evaluate the quality of the MTJ stack film without the interference of the device fabrication process.

White light-modulated bipolar resistive switching characteristics of Cu/MoS2 NRs/Pt MIM structure

The present work explores the white light controlled resistive switching functionality of MoS2 nanorods (NRs) by fabricating a metal-insulator-metal stack configuration. The Cu/MoS2 NRs/Pt/Si device demonstrates the reproducible two-state bipolar resistive switching characteristics under both dark and light environments. In the dark condition, the resistive switching behavior of the NR device could be attributed to the metallic path formation/rupture between top and bottom electrodes. Whereas the applied white light causes the lowering of SET and RESET voltages by inducing conducting path formation/rupture via electron trapping/detrapping in sulfur vacancies across the MoS2 NRs. The formation of a conducting path under dark and light illumination conditions is well explained by proposing a conceptual model and analyzing the resistance vs temperature measurements. It is observed that the white light acts as an external tool to modulate the resistive switching behavior of the fabricated NR device. The correlation between the applied light intensity and the SET voltage is also demonstrated. The NR structure of the MoS2 device provides good endurance of 1500 cycles and a long retention time of 103 s at room temperature under light illumination because of straight conducting path formation through NRs. These results demonstrate that the optically active MoS2 NR based devices have potential for next generation tunable nonvolatile resistive random access memory applications with additional functionality such as photosensors and optoelectronic switches.

Control of vortex chirality in bi-component magnetic nanodisks

In the last decade, special attention has been paid to the nucleation and control of the vortex state in magnetic nanostructures, for possible applications in nonvolatile magnetic random access memories and logic networks. Here, we study bicomponent magnetic nanodisks, in both single and 2D array arrangements, as potential storage systems where the information unit is represented by vortex chirality (magnetization rotational direction). We mainly focus on 300 nm diameter disks made of a permalloy lens and an iron crescent, with variable locations of the permalloy-iron interface. Through an extensive micromagnetic modeling analysis, we demonstrate the possibility of tuning, via the application of a magnetic field parallel to the interface, the nucleation of the vortex (always occurring in the permalloy region), its motion up to the expulsion site, and its chirality. Moreover, we find that the vortex stability is preserved over a wide field range also for strongly packed disks, due to the reduced effects of interdisk magnetostatic coupling. The main features of the magnetization reversal mechanism are preserved by reducing the disk diameter up to about 60 nm, making possible their exploitation in concept devices for magnetic encoding and logic computation.

Efficient compute node-local replication mechanisms for NVRAM-centric data structures

The long-awaited nonvolatile random-access memory technology NVRAM is finally publicly available on the market and requires significant changes to the architecture of in-memory database systems. Since such hybrid DRAM–NVRAM database systems may be able to keep the primary data solely persistent in the NVRAM, efficient replication mechanisms need to be considered to prevent base data losses and to guarantee high availability in case of various persistent memory failures. In this article, we argue for a software-based replication approach and present compute node-local mechanisms to provide the building blocks—generally available for most platforms—for an efficient NVRAM replication with a low latency and minimal throughput penalty. Within our evaluation, based on both real NVRAM hardware and DRAM-backed emulation, we measured up to 10$$\times $$ less overhead for our optimized replication mechanisms compared to the basic replication mechanism of the Intel persistent memory development kit PMDK. Finally, we present a lightweight switching approach for enabling the adaptive online selection of the best replication mechanism for a given situation.

Nanoelectromechanical Switches by Controlled Switchable Cracking

Nanoelectromechanical (NEM) switches could surmount the Boltzmann Tyranny in the current charge-carrier systems. However, thus far, practical implementations of the NEM systems have been hindered by the complicated fabrication processes of forming the extremely small air gap. Here, we realize a very simple NEM switch by exploiting a switchable nanocrack controlled by an electric field in a metallic alloy-ferroelectric heterostructure. The crack is formed in a controllable manner in terms of its initiation, location, and orientation through a bridge-like structure. The open and closed states of the crack are programmed under a cyclic electric field. In addition, an abrupt switching behavior with a nonvolatile high ON/OFF current ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ) is measured owing to the near-zero OFF-state leakage current across the crack. This simple nanocrack switch presents a novel opportunity in the NEM systems, which can be used as a new nonvolatile random-access memory and logic.

Acceleration of Storage Performance in Cloud Systems by Using NVRAM

Non-Volatile Random Access Memory (NVRAM) is anticipated to be utilized as the performance accelerator of future cloud storage systems. This article aims to analyze how large performance improvement can be expected if we use NVRAM as the performance accelerator of legacy storage subsystems. Specifically, we try to find the best employment of NVRAM with respect to storage performances. To do so, we quantify the hot storage area and replace it with NVRAM to obtain the best performances. Our analysis shows that the source of hot storage traffic is not limited to any single particular storage area, but it is different for application types executed. Specifically, journaling accesses dominate in database applications, while swapping accesses dominate in memory-intensive applications. In some applications such as video streaming, file accesses dominate. Based on these findings, we suggest the usage of NVRAM to maximize the performance improvement of cloud storage systems.

Lattice Dynamic and Instability in Pentasilicene: A Light Single-Element Ferroelectric Material With High Curie Temperature

For applications in Si-based electronics, it would be interesting and significant to induce spontaneous polarization in some allotrope of pure Si. However, because of the symmetry protection in conventional Si forms, separating positive and negative charge states is difficult. This study shows that a desired Si structure, $T$ pentasilicene, can be realized by tilting the dimers in the two-dimensional pentasilicene sheet, which not only stabilizes the system but also leads to intrinsic ferroelectricity, with a high Curie temperature of 1190 K. This Si allotrope could have potential applications in nonvolatile random-access memory.

Tunneling of photon-generated carrier in the interface barrier induced resistive switching memory behaviour

The resistive switching effect is a great physical phenomenon that the resistance of a material can be reversibly changed by applying an electric pulse, which is useful to constructing the nonvolatile resistance random access memory (RRAM) in the next generation of memory system. In this work, a sandwich structure (ITO/WO3/AZO) was prepared by using WO3 film (∼300 nm) as the dielectric layer meanwhile indium tin oxide (ITO) as the top electrode and aluminium-doped zinc oxide (AZO) as the bottom electrode. An enhanced resistive switching memory behavior was observed in the sample processed by light-illumination. Furthermore, the set voltage (Vset) and reset voltage (Vreset) are increased but the HRS/LRS resistance ratio is decreased with the increasing of illumination time for 600 °C annealed sample. Through further analysis, a physical model on the tunneling of photon-generated carrier in the Schottky barrier layer driven by electric pulse is proposed to explain the enhanced resistive switching memory behavior. The suggested mechanism is highly pivotal for the resistive switching phenomenon to be properly applied in the nonvolatile RRAM device.

Unusual Behaviors of Electric-Field Control of Magnetism in Multiferroic Heterostructures via Multifactor Cooperation.

Electric-field control of magnetism (EFCM) is very important for the exploration of high-density, fast, and nonvolatile random-access memory with ultralow energy consumption. Here, we report the electric-field-induced ferroelectric phase transitions in Pb(Mg1/3Nb2/3)0.82Ti0.18O3 (PMN-0.18PT) and symmetry breaking of EFCM behaviors for corresponding directions in multiferroic heterostructures composed of amorphous ferromagnetic Co40Fe40B20 (CoFeB) and PMN-0.18PT. We uncover a new mechanism behind the unusual phenomena, involving coupling between CoFeB and PMN-0.18PT via complex cooperation of electric-field-induced ferroelectric phase transitions, competition of different ferroelectric domains, and internal electric field in PMN-0.18PT. The deterministic EFCM with reversible and nonvolatile nature opens up a new avenue for exploring EFCM in multiferroic heterostructures and is also significant for applications.

Temperature dependence of ferroelectricity and domain switching behavior in Pb(Zr0·3Ti0.7)O3 ferroelectric thin films

Abstract Owing to their high remanent polarization, fast switching behavior, and controllable preparation process, Pb(Zr0·3Ti0.7)O3 (PZT) thin films are considered to be one of the most promising materials for non-volatile ferroelectric random access memory (FRAM). In this work, high-quality PZT thin films with a preferred (111) orientation and smooth surface are obtained by the sol–gel method. The temperature dependence of the ferroelectricity and domain switching behavior is thoroughly investigated by piezoresponse force microscopy (PFM). The domain structure undergoes distinct 180° switching and reconstruction under an external DC voltage. Polarization hysteresis loop analysis of PZT reveals that the spontaneous polarization (Ps), remanent polarization (Pr), and coercive voltage (Vc) decrease as the temperature increases from 20 to 70 °C, in agreement with the Landau classical theory of phase transition. In addition, the PFM results show that the PZT films consistently exhibit good switching behavior as the temperature increases from 23.7 to 70 °C. An increase in the piezoelectric constant (Dmax) with increasing temperature is ascribed to more rapid domain wall movement and easier domain reorientation, as predicted by thermodynamic theory. This investigation suggests that the temperature strongly affects the ferroelectricity and switching behavior of PZT thin films and offers guidance for the design of FRAM.

Tight Evaluation of Real-Time Task Schedulability for Processor's DVS and Nonvolatile Memory Allocation.

A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor’s voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18–88%.

Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy

This paper proposes a seven-transistor–two-memristor (7T2M) nonvolatile static random access memory (NVSRAM). The designed 7T2M-NVSRAM is resilient to data loss while powered off and renders substantial read/write margins as compared to the conventional SRAM and the previous NVSRAM structures. One memristor is connected to the sources of driver transistors of 6T SRAM, and the motive of this memristor is to enhance the read and write stability. It is ascertained that the read margin is improved by 16%, and the write margin is improved by 30% in regards to the conventional SRAM, whereas another memristor is connected to the data node of the 6T SRAM along with an additional transistor, and this memristor enables the nonvolatile nature. Moreover, a temperature-dependent memristor model is employed to investigate the temperature effects on power dissipation along with storing and restoring energy during power-down and power-up conditions, respectively. The results reveal that the power dissipation rises ten times for the increase of every 100 K temperature, and both storing and restoring energies decrease at higher temperatures. The designed structure strengthens the applicability of SRAM in advance processor used for temperature sensor design and also enables it to be utilized in the persistent memory design.

Design and development of memristor‐based RRAM

A power- and variability-aware non-volatile resistive random access memory (RRAM) cell is presented. Non-volatility is achieved due to the use of a memristor as a memory element, which when integrated with a carbon nanotube field-effect transistor (CNFET) helps achieve tremendous robustness against process variation. The half-select issue, inherent in the 2T2M RRAM cell (state-of-the-art design based on the memristor) have been resolved and its circuit parameters have been compared with those of the proposed cell. Also, the proposed cell has been compared with the standard 6T SRAM (S6T) cell. The proposed cell shows 1.6×/4.08× narrower read delay/write delay variability compared with 2T2M. 5CNFET2M also shows 1.8× narrower read delay variability than that of S6T. Furthermore, the proposed cell shows 6.9× shorter write delay in comparison with the 2T2M RRAM cell. 5CNFET2M consumes 10 6 ×/1.34× lower power during hold mode compared with the conventional 6T static random access memory/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared with both the cells. All the simulated data, presented here are at the nominal supply voltage of 1 V. These improvements are gained at the expense of slightly longer read time compared with 2T2M/S6T and 31.3× longer write delay compared with S6T.

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells

A new nonvolatile static random access memory (nvSRAM) design based on the multi-level cell (MLC) characteristics of resistive RAMs (RRAMs) is presented in this brief to reduce the store energy of frequent-off and instant-on applications. The data store circuitry is designed to enable the energy-efficient multi-bit data backup of every two SRAM cells into a single four-level MLC RRAM of the proposed MLC-nvSRAM cell. Precharging restore scheme is employed to reduce the restore energy by suppressing the short-circuit and leakage currents when power supply is ramping up for data restore. Optimization method of multiple resistance states is also developed to maximize the restore yield considering the CMOS and RRAM process variations. The store and restore energy of the proposed MLC-nvSRAM circuit are reduced by 53.97% and 62.61%, respectively, as compared to the lowest store and restore energy of the previously published nvSRAM circuits based on single-level cell (SLC) RRAMs.

Read‐decoupled 8T1R non‐volatile SRAM with dual‐mode option and high restore yield

This Letter proposes a read-decoupled (RD) and average 8T1R non-volatile static RAM (SRAM), RD-8T1R. It uses only one memristor to achieve 2 × store energy reduction and higher restore yield compared with other two memristors based non-volatile SRAMs. In addition, this structure can offer two alternative SRAM modes unlike previously known non-volatile SRAMs, i.e. a high speed and a stable mode. Compared with existing technologies, the simulation results in TSMC-65 nm show that the proposed scheme provides a remarkable restore yield. There are ∼ 154% improvement in the read static noise margin (@typical–typical (@TT) corner and stable mode) and ∼ 23% improvement in the read delay (@TT corner and high speed mode) compared with the previous 6T/7T/8 T non-volatile SRAMs.

Characteristics of MoS2 monolayer non-volatile memory field effect transistors affected by the ferroelectric properties of BiFeO3 thin films with Pt and SrRuO3 bottom electrodes grown on glass substrates

We investigated the characteristics of ferroelectric non-volatile random-access memory field effect transistors (MoS2-BFO NVRAM FETs) consisting of monolayer MoS2 channels, BiFeO3 (BFO) gate layers, and Pt and SrRuO3 bottom electrodes on glass substrates. As a result of the comparative experiments of the Pt and SrRuO3 bottom electrodes, it was confirmed that the BFO gate layer using the SrRuO3 bottom electrode showed a higher remanent polarization, faster switching time, and superior fatigue endurance than the BFO gate layer using the Pt bottom electrode. It is suggested that the good ferroelectric properties of the BFO gate dielectric layer on the SrRuO3 bottom electrode is resulting from its (001)-oriented growth. The MoS2 BFO NVRAM FET with a SrRuO3 bottom electrode exhibited a wider memory window than the Pt bottom electrode because the SrRuO3 bottom electrode had a higher remanent polarization of the BFO gate layer compared to the Pt bottom electrode.

Multi-agent large-scale parallel crowd simulation with NVRAM-based distributed cache

This paper presents the architecture, main components and performance results for a parallel and modular agent-based environment aimed at crowd simulation. The environment allows to simulate thousands or more agents on maps of square kilometers or more, features a modular design and incorporates non-volatile RAM (NVRAM) with a fail-safe mode that can be activated to allow to continue computations from a recently analyzed state in case of a failure. We show results for an evacuation scenario for an area of up to 6 km2 in a district of Gdansk, Poland, performed on two clusters, one with hardware simulation of NVRAM. We have shown a very small overhead of using NVRAM compared to the RAM only solution and an overhead of 20% with the fail-safe mode on using NVRAM, shown up to 30 000 agents and up to 25 000 iterations of the simulation. We also show the benefit of using NVRAM for file synchronization with a slow growth of the execution time while increasing the map size. We then present how the frequency of visualization affects execution time and very good scaling of the proposed solution in a cluster environment for more than 650 processes and 60 000 agents.

Design and implementation of skiplist-based key-value store on non-volatile memory

Non-volatile random access memory (NVRAM) is a promising approach to persistent data storage with outstanding advantages over traditional storage devices, such as hard disk drives (HDDs) and solid state drives (SSDs). Some of its biggest advantages are its DRAM-like read latency and microsecond-level write latency, which are several hundred times faster than those in the original block device. However, one of the issues with using NVRAM as a storage device is designing an indexing system for its data stores to fully utilize NVRAM characteristics. The state-of-the-art indexing systems of non-volatile key-value stores are usually based on B+-trees or their variants, which were originally designed for block-based storage devices with better sequential performance than random performance. The semantics of B+-tree require data being sorted into leaf nodes and inner nodes and frequent splitting and merging to keep balanced. However, all the sorting, splitting, and merging operations cause extra write to NVRAM, which decreases its performance. In this article, we propose NV-Skiplist, a skiplist-based indexing system for key-value stores on NVRAM that fully uses the features of both NVRAM and DRAM. NV-Skiplist constructs its bottom layer in non-volatile memory to maintain data persistence and support range scans. It builds its upper layers in DRAM to retain rapid index searching and prevent consistently large overhead. We also propose a multiranged variant of NV-Skiplist to increase its search performance and scalability. We evaluate the performance of NV-Skiplist and wB+-tree which is a state-of-art scheme on an NVRAM emulator on a server with an Intel Xeon E5-2620 v2 processor. The results show that our design outperforms the original tree-based, non-volatile key-value stores up to 48%.