Nonvolatile Logic Gates Research Articles

Ultralow-energy multiferroic majority gates via magnetostrictive heterogeneity

Multiferroic nanomagnetic technology represents a cutting-edge domain with considerable potential for advancing the frontier of ultra-low energy, high precision, and swift responsive nanomagnetic nonvolatile logic gates. This manuscript introduces an innovative majority logic gate that capitalizes on the disparate magnetostrictive responses of materials with positive and negative coefficients under uniform strain conditions, through the implementation of a heterogeneous multiferroic structure integrated with a strain clocking mechanism. Distinct from traditional nanomagnetic majority logic gates, which rely on a single material within a stairs-type global strain clocking paradigm, our proposed design realizes an order-of-magnitude reduction in energy dissipation per operational cycle. Furthermore, simulate each scenario in a thermal noise field, with different logic value inputs getting the correct output, the majority gate supports pipelining capabilities, and offers significant insights for the engineering of energy-efficient multiferroic nanomagnetic logic devices.

Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devices

Today's on-chip computing power is constrained by the “memory wall” and “power wall” caused by the Von Neumann bottleneck. As a potential solution, this work has developed nonvolatile logic gates based on field-effect tri-terminal oxide resistive switching memory devices (3T-RRAM). A compact circuit model using a polynomial control source (PCS) is proposed to describe the behavior of the fabricated 3T-RRAM. The 3T-RRAM can be regarded as a nonvolatile transmission gate for constructing nonvolatile logic gates. Additionally, a full adder with input storage functionality has been designed using only eight 3T-RRAMs (four nonvolatile logic gates), and a binarized neural network (BNN) based on 3T-RRAM logic gate arrays has been proposed. This demonstrates the great potential of nonvolatile logic gates in computing-in-memory applications.

Double magnetic tunnel junction two bit memory and nonvolatile logic for in situ computing

In exascale computing, a huge amount of data is processed in real-time. Conventional CMOS-based computing paradigms follow the read, compute, and write back mechanism. This approach consumes significant power and time to compute and store data. in situ computation – where data are processed within the memory system – is considered a platform for exascale computation. Spin transfer torque perpendicular magnetic tunnel junctions (PMTJ) is a nonvolatile memory device with several potential advantages (fast read/write, high endurance, and CMOS compatibility) to become a next generation memory solution. A double magnetic tunnel junction (DMTJ) consists of two PMTJs constructed in a vertical arrangement. In this paper, DMTJ offers the possibility of constructing not only standalone and embedded RAM but also MTJ-based VLSI computing. A DMTJ-based two bit memory cell that supports a nonvolatile logic compute paradigm is presented. The multi-level cell supports both a high speed read/write two bit memory cell and a nonvolatile logic gate that computes and stores input data in real-time.

Cascadable direct current driven skyrmion logic inverter gate

Nanoscale skyrmions enable ultralow-power nonvolatile logic gate designs due to their current-driven motion and topological protection. A key building block in skyrmion-based digital spintronics is the logic inverter (not) gate. Despite recent computational and practical demonstrations, a skyrmion-based low-power, wideband, and cascadable inverter gate is still a long way off. For skyrmion-based logic circuits, a systematic design and analysis of an inverter gate is essential. Here we present a skyrmion logic inverter design and analyze its full operation using micromagnetic modeling. Because of the substrate thermal conductivity, our investigations reveal that the all-metallic inverter gate can function with direct current drive, wide bandwidth, submicron footprint, no or low external magnetic field, cascadability, and with room-temperature thermal stability despite Joule heating. Using magnetic insulators for eliminating Joule heating and lowering the exchange stiffness, magnetic moment and other factors might further assist in reducing power consumption by more than four orders of magnitude.

A giant magnetoimpedance effect based nonvolatile Boolean logic gate

The biphase magnetic heterostructure (Ni/Fe20Ni45Co25Si2B8/micro-planarcoil/Fe20Ni45Co25Si2B8/micro-planar coil/Fe20Ni45Co25Si2B8/Ni) bonded with a pair of thin magnets shows an improved asymmetric and hysteretic giant magnetoimpedance (GMI) effect with respect to an external dc magnetic field. This is attributed to the modification of the soft amorphous magnetic alloy’s (Fe20Ni45Co25Si2B8) permeability by the hysteretic magnetostrictive stress from the neighboring magnetostrictive Ni layer besides the magnetostatic coupling. More importantly, nonvolatile logic gates, such as NOR and NAND, can be implemented with either a single GMI laminate or arrays. On one hand, after applying two sequential magnetic field pulses as the logic inputs to a single proposed laminate, the nonvolatile output voltages are positive high (logic 1) or positive low (logic 0) depending on the signs and magnitudes of pulses. On the other hand, after applying the magnetic field pulses parallel to the GMI laminates arrays, different logic functions can be programmed and realized at run-time. The integration of memory and logic functions enables the proposed GMI laminate to be a possible candidate for future computing systems beyond von Neumann architecture.

Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware

A nonvolatile logic gate based on magnetic tunnel junction-based nonvolatile logic-in-memory (NV-LIM) architecture is designed for the implementation of compact and low-power binary neural network (BNN) hardware. The use of NV-LIM architecture for designing BNN hardware makes it possible to reduce both computational and data transfer costs associated with inference functions of deep neural networks. Through an experimental evaluation of a basic component of BNN hardware designed with NV-LIM architecture, we demonstrate that a nonvolatile logic gate designed and optimized based on its quantitative analysis can reduce the circuit area to 32% of a conventional structure as well as reduce the average power consumption assuming intermittent operation in sensor node applications to 14%.

Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration

The high power and the long global interconnect delay are two of the major bottlenecks that limit the further scaling down of the process nodes in the VLSI systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and the interconnect delay. Current-induced magnetic domain-wall (DW) racetrack memory (RM) has the advantages of nonvolatility, fast switching speed, and high density. It may offer opportunities to open a new paradigm of circuits and architectures to significantly alleviate the power and delay issues. This paper presents the magnetic DW RM-based new nonvolatile logic designs for the low-power computing and fast run-time-reconfiguration. Both data transfer and reconfiguration are achieved by shifting the magnetic strips. Verify-before-shift approach is used to greatly reduce the shifting energy. Compared with the conventional nonvolatile logic gate, the proposed nonvolatile logic scheme doubles the operating speed with 87% lower operating energy. Moreover, the proposed nonvolatile logic gates can be reconfigured after fabrication, which makes the designs more flexible and robust. The reference reconfiguration and the polarity reconfiguration are presented in this paper, which can be finished in 1 ns with 130 fJ/strip energy and 6 ns with 390 fJ/strip energy, respectively.

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

Emerging non-volatile memories (NVM) based on resistive switching mechanism (RS) such as STT-MRAM, OxRRAM and CBRAM etc., are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g., > 1012) beyond mainstream NVMs, which allow them to be embedded directly with logic units for computing purpose. This integration could increase significantly the power/die area efficiency, and then overcome definitively the power/speed bottlenecks of modern VLSIs. This paper presents firstly a theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL). Special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs. To validate this study, we simulated a non-volatile full-adder (NVFA) with two types of NVMs: STT-MRAM and OxRRAM by using CMOS 40 nm design kit and compact models, which includes related physics and experimental parameters. They show interesting power, speed and area gain compared with synchronized CMOS FA while keeping good reliability.