Nonvolatile Latch Research Articles

Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysis.

In recent years, non-volatile memory elements have become highly appealing for memory applications to implement a new class of storage memory that could replace flash memories in sequential logic applications, with features such as compactness, low power, fast processing speed, high endurance, and retention. The memristor is one such non-volatile element that fits the fundamental blocks of sequential logic circuits, the latch and flip-flop; hence, in this article, a non-volatile latch architecture using memristor ratioed logic (MRL) inverter and CMOS components is focused, with an additional memristor as a memory element. A Verilog-A model was used to create the memristor element. The simulation findings validated the compact, low-voltage, and reliable design of the latch design. We evolved in technology enough to create a master-slave flip-flop and arrange it to function as a counter and a shift register. Power, number of elements, cell size, energy, programming time, and robustness are compared to comparable non-volatile topologies. The proposed non-volatile latch proves non-volatility and can store data with a 24% reduction in power consumption and a near 10% reduction in area.

A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications

A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS

Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory Applications

Spin transfer torque (STT) based magnetic tunnel junction (MTJ) device is a commercially appealing option for non-volatile latches and flip-flops. In this paper, an STT-MTJ based non-volatile latch with auto-writeterminate (AWT) feature is proposed. The proposed latch has a simple structure, better stability, and higher speed, and is easy to integrate with CMOS logic styles. Also, no additional write driver circuit is needed, resulting in a smaller footprint while writing into the MTJs. Therefore, the proposed latch consumes less power than earlier latches while using fewer transistors for a write operation and logic implementation. The proposed AWT circuit continuously monitors the write operation and prevents redundant MTJ writing and removes excessive write current flow, thereby saving write energy. The AWT circuitry can save the total write energy by ~83% when compared to the conventional write circuit. Also, the proposed circuitry for self-write termination uses 75% fewer transistors compared to previously proposed circuits.

A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design.

In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions.

Non-Volatile Latch Compatible With Static and Dynamic CMOS for Logic in Memory Applications

To overcome the performance bottleneck of the CMOS-only logic circuits, logic-in-memory (LiM)-based circuits can be used. Herein, the memory and logic are combined to reduce the power requirements and the data access delay. The LiM architecture is proposed to be better in terms of efficiency when compared to the Von-Neumann architecture which is currently being used. In this article, a novel non-volatile (NV) latch is proposed to realize the LiM-based computation. It is compared with previous circuit architectures of the NV latch. The proposed latch consists of multiple magnetic tunnel junctions (MTJs) connected in series which are accessed through an NMOS transistor for reading the data. A cross-coupled inverter (CCI) is used to regenerate the output to the appropriate logic levels using its inherent regenerative action. The proposed latch has a simple design, higher stability, and lower tunnel magnetoresistance (TMR) degradation, and compatibility with static and dynamic CMOS logic styles. Furthermore, the proposed latch is having fewer transistor count in logic implementation which result in minimized area overhead and lower power consumption. The existing write circuit is also modified for writing the MTJs in the proposed NV latch which results in a 29.57% reduction in power consumption for a write margin of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$20 ~\mu \text{A}$ </tex-math></inline-formula> and 34.92% for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40 ~\mu \text{A}$ </tex-math></inline-formula> write margin. Furthermore, the area requirement of the modified write circuit is found to be significantly lower than that of the existing write circuit.

A radiation-hardened hybrid RRAM-based non-volatile latch

In this paper, a radiation-hardened resistive random-access memory (RRAM)-based non-volatile (NV) latch with a dual-interlocked storage cell is proposed and analyzed. The single-event effects of the proposed NV latch are simulated and discussed. Simulations of the proposed element are based on a 0.18 μm complementary metal-oxide-semiconductor design kit for the peripheral circuit and the voltage threshold adaptive memristor model for the RRAM. The simulation results indicate that the injected charge to induce a single-event upset (SEU) of the proposed NV latch is above 4.5 pC. As compared to the traditional RRAM based NV latch, the proposed NV latch is relatively immune to an SEU. This immunity from the SEU originates from the redundant storage nodes and interlocked feedback mechanism. Moreover, the area overhead of the proposed NV latch (eight transistors in the core storage element) are much lower than other radiation-hardened technology, e.g. TMR or FERST.

An optimization of a non-volatile latch using memristors for sequential circuit applications

An optimization of a non-volatile latch using memristors for sequential circuit applications

Retention characteristics of a nonvolatile latch utilizing a ferroelectric transistor

This paper presents retention characteristics and design recommendations for a nonvolatile latch circuit based on a ferroelectric field-effect transistor. In the design, the use of a ferroelectric transistor in a resistive load inverter allows tuning of the circuit for each ferroelectric transistor size. An estimate of the retention time, due to the unique polarization properties of the ferroelectric layer at the gate, is provided for each transistor size. Data collected for three transistor sizes display the possibility of retaining a stored value beyond a 10-year period, with various size transistors indicating 13–38-year retention periods. Switching the ferroelectric layer polarization between two distinct states by applying either negative or positive poling voltages to the gate of the ferroelectric transistor is explored. Experimental results are presented for each transistor, and detailed retention predictions are shown by measured and extrapolated data. Design parameter recommendations are made for optimization of the retention time of the circuit depending on the transistor size.

An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual $V_{\mathrm {ref}}$ sensing scheme (DVSS) that selectively uses an optimal $V_{\rm {ref}}$ between $V_{\rm {ref+}}$ and $V_{\rm {ref-}}$ is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal $V_{\rm {ref}}$ is selected after fabrication, and the calibrated switch control bit, which contains $V_{{\rm {ref}}}$ selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with $2\times $ faster sensing speed and $1.5\times $ lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

Circuit Models for Ferroelectrics—Part II: Analysis of FE-Nonvolatile Latches

We present a detailed analysis of hybrid ferroelectric (FE)-CMOS nonvolatile latches, based on simulations with the unified physical circuit model from Part-I and experimental verification with circuit measurements. Hybrid FE-CMOS latches are categorized into three classes by the circuit topology of the readout operation. The effect of the physical model parameters is studied in all regions of operation by a variational analysis. Design intuition for the signal timing and sensing margin is provided and the strategies for the design optimization are discussed. Signal degradation due to imprint and fatigue in each latch topology is also compared.

Circuit Models for Ferroelectrics—Part I: Physics of Polarization Switching

We present a physical circuit model of ferroelectric (FE) polarization switching for the analysis and design of hybrid FE-CMOS circuits. Stochastic geometry is applied to domain nucleation, growth, and coalescence under arbitrary voltage and current input signals. The circuit model is first constructed for ideal FE capacitors and then extended to the realistic effects of lateral scaling, anisotropic growth, and disorder in polycrystalline films. Reliability degradation by imprint and fatigue is also incorporated. The interaction of model parameters and circuit design for three different nonvolatile latch topologies is presented in Part II.

Implementation of low‐power, non‐volatile latch utilising ferroelectric transistor

The implementation of a non-volatile latch circuit developed with a metal–ferroelectric–semiconductor field-effect transistor is presented. The circuit contains two inverter stages in order to create and rectify the desired waveform. The hysteresis properties of the ferroelectric transistor allow it to retain a polarisation state after an applied voltage at the gate is removed. This circuit has reduced power requirements because a constant power supply is not needed at all times; instead, a voltage is only needed at the gate of the ferroelectric transistor when storing a value, and the other components only need a power supply when reading the stored value from the circuit. The circuit is less complex than similar non-volatile latches because only a single ferroelectric transistor is used and fewer overall transistors may be used. It also has the advantage of being radiation-hardened for space applications.

MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure

We present two non-volatile flip-flops (NVFFs) that incorporate magnetic tunnel junctions (MTJ) to ensure fast data storage and restoration from intentional and unintentional power outages. The proposed designs also facilitate enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The proposed NVFF eliminates additional write drivers, and can operate at up to 2 GHz at 1.1 V, with 0.55 pJ of energy consumption in 22 nm predictive technology. We also address the issue of write asymmetry of MTJ through careful transistor upsizing to achieve near uniform write latency. A data-dependent power gating technique is proposed to mitigate the high static current during retention and back-to-back writing of the identical input data. The proposed gated NVFF achieves several orders of magnitude energy saving at the expense of 1.56X area compared to a standard enhanced scan flip-flop.

Temperature Effects on a Non-Volatile Memory Device with Ferroelectric Capacitor

The temperature effects on a ferroelectric non-volatile memory latch were measured. The device is based on a design from Radiant Technologies Inc. utilizing a discrete ferroelectric capacitor. The effects measured include functionality, I-V characteristics and retention. The range of temperatures for which the device was tested is –107°F to +302°F. The results are compared with measurements made at room temperature for the device. Retention measurements of the device at elevated temperatures allow predictions of retention performance under normal operating conditions. Potential applications of this device in harsh environments which include aerospace, industrial and automotive are presented.

Hardening Techniques for MRAM-Based Nonvolatile Latches and Logic

Magnetic RAM (MRAM) is considered as a promising nonvolatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. Thanks to its fast speed, easy integration with CMOS and infinite endurance, MRAM has been proposed to build up nonvolatile latches and logic circuits to overcome the power challenge of conventional CMOS circuits. However, they are vulnerable to single event effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are described in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on configurable logic block (CLB) to mitigate SET on data paths. By using 65 nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness and performance.

Memristor Logic Operation Gate With Share Contact RRAM Cell

In this letter, we proposed a novel operation of a share contact resistive random access memory (CRRAM) structure to realize a nonvolatile latch (NV latch) with a single transistor. With a share CRRAM structure and sequential input operations, the NV latch as well as and/ or functions have been successfully demonstrated. The new mixing approach of combining memory and logic in a single unit projects the possibility of new applications for VLSI circuits.

Fast Pulse Driving of Ferroelectric SBT Capacitors in a Nonvolatile Latch

We demonstrate a fast shutdown and resumption of a logic circuit applied a nonvolatile latch having SrBi 2 (Ta,Nb) 2 O 9 (SBT) capacitors without a higher drive voltage than a logic voltage of 1.8 V. By assigning an individual drive circuit of the SBT capacitors to the nonvolatile latch not sharing a drive circuit with multiple nonvolatile latches, the fast shutdown and resumption of a logic circuit were completed in 7.5 ns at a drive voltage of 1.3 V. The fast shutdown and resumption without an addition of a high drive voltage to a logic circuit meets a requirement from power-saving applications of system LSIs fabricated in CMOS technologies at 90-nm and below.

Ferroelectric Non-Volatile Logic Devices

The reduction of the power consumption is becoming more essential for portable systems. A powering down scheme is very useful to reduce power comsumption of LSIs. The scheme needs to keep logic state, so several latch circuits have been reported. However, these methods require large additional circuit or special manufacturing process. A non-volatile latch with ferroelectric capacitors is simple and smart way [1], and its area penalty is very small. The non-volatile device needs no power supply for data keeping. Moreover, a dynamic reconfigurable logic can be possible by using the non-volatile latch as non-volatile switches.

Ferroelectric Non-Volatile Logic Devices

Ferroelectric non-volatile logic is proposed. It is low power and can be used for dynamic reconfigurable logic technologies by storing logic state or circuit configuration non-volatility. Cost of LSIs can be decreased by switching circuit blocks. The fundamental device of non-volatile latch was developed and characterized. Moreover, advanced functional device that can do operation at a ferroelectric capacitor was also fabricated. The durability and the low power consumption were confirmed.