Abstract
We present a detailed analysis of hybrid ferroelectric (FE)-CMOS nonvolatile latches, based on simulations with the unified physical circuit model from Part-I and experimental verification with circuit measurements. Hybrid FE-CMOS latches are categorized into three classes by the circuit topology of the readout operation. The effect of the physical model parameters is studied in all regions of operation by a variational analysis. Design intuition for the signal timing and sensing margin is provided and the strategies for the design optimization are discussed. Signal degradation due to imprint and fatigue in each latch topology is also compared.
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