Charge-trapping Nonvolatile Memory Research Articles

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks.

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells-e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.

Solution-processed zirconium acetylacetonate charge-trap layer for multi-bit nonvolatile thin-film memory transistors

ABSTRACT The charge trap property of solution-processed zirconium acetylacetonate (ZAA) for solution-processed nonvolatile charge-trap memory (CTM) transistors is demonstrated. Increasing the annealing temperature of the ZAA from room temperature (RT) to 300°C in ambient, the carbon double bonds within the ZAA decreases. The RT-dried ZAA for the p-type organic-based CTM shows the widest threshold voltage shift (∆VTH ≈ 80 V), four distinct V THs for a multi-bit memory operation and retained memory currents for 103 s with high memory on- and off-current ratio (IM,ON/IM,OFF ≈ 5Ⅹ104). The n-type oxide-based CTM (Ox-CTM) also shows a ∆V TH of 14 V and retained memory currents for 103 s with I M,ON/I M,OFF ≈ 104. The inability of the Ox-CTM to be electrically erasable is well explained with simulated electrical potential contour maps. It is deduced that, irrespective of the varied solution-processed semiconductor used, the RT-dried organic ZAA as CTL shows the best memory functionality in the fabricated CTMs. This implies that the high carbon double bonds in the low-temperature processed ZAA CTL are very useful for low-cost multi-bit CTMs in flexible electronics.

Non-volatile charge-trap memory characteristics with low-temperature atomic layer deposited HfO2−x charge-trap layer and interfacial tunneling oxide formed by UV/ozone treatment

Non-volatile charge-trap memory characteristics were investigated in the thin-film transistors with an indium-gallium-zinc oxide channel and an oxygen-deficient hafnium oxide (HfO2−x) charge-trap layer deposited by atomic layer deposition (ALD). The HfO2−x charge-trap layer was subsequently UV/ozone treated to convert its surface to more insulating tunneling oxide. The HfO2−x charge-trap layer deposited at a low temperature of 50 °C was found to have a high defect density to store electrons with an areal density of 1.57 × 1012 cm−2 calculated from the threshold voltage (VT) shift of 30 V. The VT shifted positively as a result of electron charging in the charge-trap layer by applying positive gate bias, and then reduced back reversibly by applying negative bias. Also, the shifted VT is retained over time, rendering non-volatile memory characteristics. The improved reliability of charge storage is expected to come from eliminating trap states at the interface by UV/ozone treatment. It also simplifies the overall fabrication process by removing additional processing steps of tunneling oxide layer deposition. The proposed device turned out to have a large memory window thanks to the high trap density in the HfO2−x charge-trap layer deposited by low-temperature ALD and the good non-volatility by using UV/ozone treatment.

Black phosphorus unipolar transistor, memory, and photodetector

We report the fabrication, electrical, and optical characterizations of few-layered black phosphorus (BP)-based field-effect transistor (FET). The fabricated device exhibits a p-type transport with hole mobility up to 175 cm2 V−1 s−1 at Vds = 1 mV. The transfer characteristics show a large hysteresis width that depends linearly on the gate voltage and decreases with the increasing drain bias. The fabricated device also ensures a non-volatile charge-trap memory behaviour, with a stable and long retention time. The material’s photodetection capabilities enhance the functionality of the device making it controllable by light. The photocurrent was observed to be linearly increasing with the light incident power and exposure time. As a photodetector, the transistor reaches a responsivity and detectivity up to 340 mA W−1 and 6.52 × 1011 Jones under white light at 80 mathrm{mW}, respectively. Time-resolved measurements provide evidence of a long single exponential decay process through deep intra-gap states. Our results highlight the potential of a few layers BP as a nanomaterial for field-effect, memory, and optoelectronic devices.Graphical

An organic ambipolar charge trapping non-volatile memory device based on double heterojunctions

An organic ambipolar charge trapping non-volatile memory device is proposed based on tris(8-hydroxy quinoline) aluminum(Alq3)/ fullerene(C60)/pentacene double heterojunctions. The double heterojunctions were analyzed and compared with the sole heterojunction. Even though the Alq3/pentacene sole heterojunction shows a negative threshold voltage shift for programming under negative biasing, light illumination is required to efficiently erase. In contrast, for C60/pentacene sole heterojunction, the negative shift of threshold voltage is observed even with a positive erasing voltage. By combining the two trapping layers, a large memory window with fully-electrical programming and erasing is obtained. The efficient programming and erasing of the double heterojunctions structure are analyzed, sufficient electrons can be injected that enables the electrical erasing, and the negative shift of the threshold voltage under positive erasing voltage for the C60/pentacene structure is suppressed due to the suppression of the large built-in potential for the sole heterojunction, which can be verified by a large positive shift for the pentacene/C60/pentacene double heterojunctions.

An InGaZnO Charge-Trapping Nonvolatile Memory With the Same Structure of a Thin-Film Transistor

A new charge-trapping nonvolatile memory (NVM) with a fully same structure to thin-film transistor (TFT) is investigated. Different from the conventional NVM with block layer/charge-trapping layer/tunneling layer stack for charge storage, this NVM uses the metal-hydroxyl (M-OH) defect at the back channel for charge storage, which forms by the reaction of IGZO with moisture and acts as acceptor-like deep-level traps. Devices with various M-OH contents are prepared by changing thermal treatment. The device with high M-OH content displays good NVM performance in terms of its large memory window (1.5 V at ±10 V, 1s), high program/erase speeds (1.1 V at 10 V, 1 ms) and good data retention (78.9% retention after 10 years); for comparison, the device with low M-OH content exhibits good TFT characteristics in terms of its small sub-threshold swing (226 mV/dec), high carrier mobility (8.1 cm2/V.s) and good electrical stability (memory window ~ 0.2 V at ±10 V, 1s). Since the NVM and TFT have the same structure, both the devices can be simultaneously prepared combined with an extra treatment to modulate the M-OH content at the back channel, thus contributing to system-on-panel development.

Erase Speed Enhancement with Low Power Operation by Incorporating Boron Doping

In this paper, it is shown that the erase efficiency of the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type nonvolatile charge trapping memory (CTM) is greatly improved by adjusting boron doping. Tunnel FET (TFET) based SONOS memory, which has p-type at source side, is superior to MOSFET based SONOS memory in terms of hole supplement and erase speed. In order to discover the specific physical reasons of this erase speed enhancement, MOSFET based SONOS memory devices with different body doping concentration are additionally investigated. As a result, it is found that the more hole supplement from source side in TFET and body side in MOSFET accelerates the erase speed and erase speed enhancement can be realized by utilizing boron doping. Furthermore, erase speed depending on device geometry, in terms of source-to-gate overlap length and gate length, is also analyzed. Interestingly, it is demonstrated that source overlap technique, which has been implemented for suppression of ambipolar current, is also possible to accelerate erase speed.

High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS₂ nFET and Nonvolatile Charge-Trap Memory

The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( $\text{R}_{\text {ON}}$ ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max–min ratio ( ${G}_{\text {MAX}}/ ~{G}_{\text {MIN}}$ ; ~50), low nonlinearity of $\alpha _{\text {p}}$ = −0.81 and $\alpha _{\text {d}}$ = −0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.

Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si structure

In this paper, we demonstrate retention improvement in nonvolatile charge-trapping memory cells by tunneling oxide engineering with Al2O3. By utilizing SiO2/Al2O3/SiO2 layers for the tunneling oxide, it is shown that the threshold voltage window after 10 years is significantly improved from 0.78 V to 4.18 V through Synopsys Sentaurus technology computer-aided design simulation. In addition, retention improvement from incorporating SiO2/Al2O3/SiO2 tunneling layers is compared with that using SiO2/Si3N4/SiO2 tunneling layers. The relationship between charge-trapping layer thickness and trapped charge emission is also investigated. As a result, we open up the possibility of using HfO2 as a charge-trapping layer with significant reliability enhancement.

Design of high performance MoS2-based non-volatile memory via ion beam defect engineering

Nonvolatile charge trap memory is an important part of the continuous development of information technology. As a 2-dimensional (2D) material with fantastic physical characteristics, molybdenum disulfide (MoS2) has been receiving extensive attention for its potential applications in electronic devices. However, while various attempts have been made to devise its charge-trap gate stack, it’s still impossible to avoid a certain performance degradation. Here, a MoS2-based nonvolatile charge trapping memory device with a charge-trap gate stack formed by implanting N ions into SiO2 is reported. The fabricated N-implanted memory devices with the energy of 6.5 keV and the dose of 1 × 1015 ions cm−2 exhibit a high on/off current ratio up to 107, a large memory window of 9.1 V, and a high program/erase speed of 10/100 µs. Moreover, the memory device shows an excellent cycling endurance of more than 104 cycles. By combining the MoS2 channel with the N-implanted charge-trap gate stack, this research opens up a fascinating field of nonvolatile charge trap memory devices.

A Graphene Oxide Quantum Dots Embedded Charge Trapping Memory With Enhanced Memory Window and Data Retention

Graphene oxide quantum dots (GOQDs) are integrated with a charge trapping layer in a nonvolatile charge trapping memory. The device structures of Pd/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /ZHO/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si and Pd/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /ZHO/GOQDs/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si are fabricated, measured, and compared. The GOQD-embedded device demonstrates improved memory window size and data retention characteristics. Under a gate sweeping voltage of ±5 V, the memory window of a GOQD-embedded device is 1.67 V, which is 35.7% larger than the same device without using GOQDs. After a retention time of 1.08×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s, the GOQD-embedded device shows only 1.2% and 3.8% decay in the high-state and low-state capacitances, respectively. The data retention loss of a GOQD-embedded device is reduced by at least 65% when compared to its counterpart, respectively.

Performance Enhancement for Charge Trapping Memory by Using Al2O3/HfO2/Al2O3 Tri-Layer High-κ Dielectrics and High Work Function Metal Gate

In this work, we have fabricated and systematically characterized a type of charge trapping memory (CTM) device with Al2O3/HfO2/Al2O3 tri-layer high-κ dielectric stacks and high work function tungsten metal gate (named as MAHAS in short). The extracted interface state density (Dit) value for the MAHAS memory is comparatively low owing to the optimized high-κ/Si interface quality using SiO2 ultrathin film (∼10 Å) grown by deionized water/O3. The MAHAS memory devices demonstrate desirable memory effects, especially significantly improved program and erase (P/E) speed. A large hysteresis memory window of 5.4 V by ± 10 V sweeping voltage and ∼2.7 V flat-band voltage shift by programming at +7 V for 100 μs are obtained. With respect to memory reliability, the MAHAS memory shows negligible memory window degradation after 106 P/E cycles, and the memory window retains 72.4% of the originally stored charge even after 105 s’ retention. With the simple structure and improved operation efficiency, the proposed MAHAS memory device is promising for future nonvolatile charge trapping memory applications.

Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates**Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02303007, the National Key Research and Development Program of China under Grant No 2016YFA0301701, and the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No 2016112.

A novel high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ∼4 V, a small leakage current density of ∼2 × 10−6 Acm−2 at a gate voltage of 7 V, a high charge trapping density of 1.42 × 1013 cm−2 at a working voltage of ±10 V and good retention characteristics are observed. Furthermore, the programming ( at 10 V for 10 μs) and erasing speeds ( at −10 V for 10 μs) of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications.

A Dynamically Reconfigurable Ambipolar Black Phosphorus Memory Device.

Nonvolatile charge-trap memory plays an important role in many modern electronics technologies, from portable electronic systems to large-scale data centers. Conventional charge-trap memory devices typically work with fixed channel carrier polarity and device characteristics. However, many emerging applications in reconfigurable electronics and neuromorphic computing require dynamically tunable properties in their electronic device components that can lead to enhanced circuit versatility and system functionalities. Here, we demonstrate an ambipolar black phosphorus (BP) charge-trap memory device with dynamically reconfigurable and polarity-reversible memory behavior. This BP memory device shows versatile memory properties subject to electrostatic bias. Not only the programmed/erased state current ratio can be continuously tuned by the back-gate bias, but also the polarity of the carriers in the BP channel can be reversibly switched between electron- and hole-dominated conductions, resulting in the erased and programmed states exhibiting interchangeable high and low current levels. The BP memory also shows four different memory states and, hence, 2-bit per cell data storage for both n-type and p-type channel conductions, demonstrating the multilevel cell storage capability in a layered material based memory device. The BP memory device with a high mobility and tunable programmed/erased state current ratio and highly reconfigurable device characteristics can offer adaptable memory device properties for many emerging applications in electronics technology, such as neuromorphic computing, data-adaptive energy efficient memory, and dynamically reconfigurable digital circuits.

Charge Trap Memory Based on Few-Layer Black Phosphorus and High-K Materials

Due to the unique properties of the two dimensional material, it has great potential for future information technology devices. Based on field-effect transistors with large hysteresis, consisting of a few-layer black phosphorus channel and a three dimensional (3D) Al2O3/HfO2/Al2O3, we successfully made the nonvolatile charge-trap memory devices. Because of the extraordinary trapping ability of the high-k HfO2, an unprecedented memory window exceeding 12 V is obtained. The device shows a high endurance of over 120 cycles and a stable retention of ∼30% charge loss after 10 years, even lower than the reported MoS2 flash memory. The high program/erase current ratio, large memory window, stable retention and high on/off current ratio, provide a promising route towards flexible and transparent memory devices utilizing atomically thin two-dimensional materials. The combination of 2D materials with traditional high-k charge-trap gate stacks opens up an exciting field of nonvolatile memory devices[1]. References (1) Qi Feng, Faguang Yan, Wengang Luo and Kaiyou Wang, Nanoscale, 8(2016)2686.

Formation of ZnO Nanoparticles by Atomic Layer Deposition for the Nonvolatile Memory Thin-Film Transistor Applications

Charge-trap-type memory device employing oxide-semiconductor charge-trap layers (CTL), such as ZnO and In-Ga-Zn-O (IGZO), have been intensively investigated for nonvolatile memory TFT applications [1]. Although encouraging device characteristics could be obtained for the proposed memory TFT, they can be expected to be far improved by using nano-particle (NP) mono-layers as alternative CTLs thanks to their isolated structures. So far, various methods such as spray pyrolysis and high-temperature-assisted self-assembly have been suggested to form discrete NP mono-layers [2]. However, low controllability in areal density of NPs and high process temperature limit device performance as well as process compatibility on flexible substrate.In this work, we propose a low-temperature atomic-layer-deposition (ALD) process for the formation of ZnO NPs with an island-growth mechanism and fabricated the memory TFTs using the ZnO-NP CTLs. We also investigate the effects of ALD conditions for the ZnO NPs on the device performance of the fabricated ZnO-NP memory TFTs (NP-MTFT). The gate-stack structure of top-gate NP-MTFTs were designed as In-Sn-O (ITO) gate electrode (150 nm)/Al2O3 blocking oxide (50 nm)/ZnO NP CTL/Al2O3 tunneling layer (10 nm)/IGZO active channel layer (20 nm)/ITO source-drain electrode (100 nm). ALD cycles for the ZnO NPs were varied to 5, 20, 30, and 40 and the deposition temperature was modulated from 100 to 190oC to investigate the effects of ALD conditions on the island formation of ZnO NPs. Diethylzinc (DEZn) and H2O was used as Zn and O precursors, respectively. The size and areal density of the ZnO NPs prepared at 160oC with 20 ALD cycles were estimated to be approximately 33 nm and 3×109 cm-2, respectively. It was interesting to note the changes in arithmetic average of surface roughness (Ra) at various ALD temperatures when the ALD cycles increased from 5 to 20 cycles. The variations in Ra were summarized to be from 0.24 to 0.28 nm at 100oC, from 0.26 to 0.40 nm at 130oC, from 0.98 to 2.13 nm at 160oC, and from 0.21 to 0.22 nm at 190oC. Consequently, it was found that the island growth of ZnO NPs could not be available at 100 and 190oC. On the other hand, at 160oC, the ZnO NPs could be successfully formed with appropriate deposition rate with increasing the ALD cycles.The NP-MTFTs employing these ZnO NP CTLs exhibited typical charge-trap nonvolatile memory device behaviors. The memory window (MW) width of the fabricated NP-MTFTs monotonously increased with increasing the ALD cycles from 0.6 to 14.6 V when VGS was swept in the forward and reverse directions in the range of ±20V at a drain bias (VDS) of 0.1 V. The MW (12.2 V) of the NP-MTFT drastically was increased for the 20-cycle device compared with that for the 5-cycle device. This result suggests that the areal density of ZnO NPs could be effectively modulated by controlling the ALD cycles of DEZ between 5 and 20 cycles. The on- and off-program characteristics of the NP-MTFTs were evaluated as a function of program voltage pulse width. The read-out operations were performed at VGS of -2 V and VDS of 0.1 V. The ratios of programmed IDS of on-states to that of off-states (Ion/Ioff) were obtained as more than 3×107 and did not experienced marked degradation when the program pulse width decreased from 1 s to 1 µs. These results suggest that the proposed NP-MTFT exhibited nonvolatile memory operations with wide memory window and high-speed program time. This is the first demonstration for the NP-MTFTs using the ALD-assisted ZnO-NP CTLs. Flexible memory device will be fabricated as future works and detailed device characteristics will be discussed at the presentation. [1] S. J. Kim, W. H. Lee, C. W. Byun, C. S. Hwang, and S. M. Yoon, IEEE Electron. Dev. Lett. 36 (11) 1153, 2015.[2] Z. Liu, C. H. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron. Dev. 49 (9), 1606, 2002.

Process Optimization and Device Characterization of Nonvolatile Charge Trap Memory Transistors Using In–Ga–ZnO Thin Films as Both Charge Trap and Active Channel Layers

Charge-trap memory thin-film transistors (CTM-TFTs) using In-Ga-ZnO (IGZO) thin films as active channel and charge trap layers (CTLs) were fabricated and characterized. Technical strategies to optimize the device design parameters were categorized into the following three parts. At first, P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O2</sub> conditions during the sputtering deposition of IGZO CTL were varied to 1%, 2%, and 5% to modulate the electronic natures of the IGZO films. The device using the CTL deposited at P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O2</sub> of 1% obtained the largest memory window and exhibited the fastest program speed. Second, to investigate the thickness effects of double-layered tunneling oxide, the configuration was varied to 3/3 nm and 5/5 nm. From the viewpoints of process window, the 5/5 nm configuration was chosen for stable device characteristics. At last, the effects of CTL thickness, which affects the number of trap sites and carrier concentration of the film, was carefully investigated. A 30-nm-thick CTL showed most desirable behaviors, including superior memory operation and uniformity. The CTM-TFTs fabricated with optimum conditions exhibited the memory margin in programmed currents between ON-and OFF-states of 2.9 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> at 1-μs program voltage pulses with ±20 V. Furthermore, the ION/OFF of five-orders-of-magnitude was obtained even after the lapse retention time for 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s.

Improved memory characteristics of charge trap memory by employing double layered ZrO2 nanocrystals and inserted Al2O3

The charge trap memory capacitors incorporating a stacked charge trapping layer consisting of double layered ZrO2 nanocrystals (NCs) and inserted Al2O3 have been fabricated and investigated. It is observed that the memory capacitor with stacked trapping layer exhibits a hysteresis window as large as 14.3 V for ±10 V sweeping gate voltage range, faster program/erase speed, improved endurance performance, and good data retention characteristics with smaller extrapolated ten years charge loss at room temperature and 125 °C compared to single layered NCs. The special energy band alignment and the introduced additional traps of double layered ZrO2 NCs and inserted Al2O3 change the trapping and loss behavior of charges, and jointly contribute to the remarkable memory characteristics. Therefore, the memory capacitor with a stacked charge trapping layer is a promising candidate in future nonvolatile charge trap memory device design and application.

A comparative study of charge trapping in HfO2/Al2O3 and ZrO2/Al2O3 based multilayered metal/high-k/oxide/Si structures

The electrical properties of multilayered HfO2/Al2O3/HfO2/SiO2 and ZrO2/Al2O3/ZrO2/SiO2 metal-oxide semiconductor capacitors were investigated in order to evaluate the possibility of their application in charge-trapping non-volatile memory devices. The stacks were deposited by reactive radiofrequency magnetron sputtering on Si substrates with thermal SiO2 with a thickness ranging from 2 to 5nm. Both types of stacks show negative initial oxide charge and its density is higher for HfO2-based structures. Memory window up to 6V at sweeping voltage range of ±16V was obtained for HfO2-based stacks. The hysteresis in these structures is mainly due to a trapping of electrons injected from the Si substrate. The charge-trapping properties of ZrO2-based samples are compromised by the high leakage currents and the dielectric breakdown. The conduction through the capacitors at low applied voltages results from hopping of thermally excited electrons from one isolated state to another. The energy depth of the traps participating in the hopping conduction was determined as ~ 0.7eV for the HfO2-based layers and ~ 0.6eV for ZrO2-based ones, originating from negatively charged oxygen vacancies. At high electric fields, the current voltage characteristics were interpreted in terms of space charge limited currents, Fowler–Nordheim tunneling, Schottky emission, and Poole–Frenkel mechanism. The charge retention characteristics do not depend on the thickness of the tunnel SiO2.

Light-bias coupling erase process for non-volatile zinc tin oxide TFT memory with a nickel nanocrystals charge trap layer

A nonvolatile charge trapping memory is demonstrated on a thin film transistor (TFT) using a solution processed ultra-thin (~7 nm) zinc tin oxide (ZTO) semiconductor layer with an Al2O3/Ni-nanocrystals (NCs)/SiO2 dielectric stack. A positive threshold voltage (VTH) shift of 7 V is achieved at gate programming voltage of 40 V for 1 s but the state will not be erased by applying negative gate voltage. However, the programmed VTH shift can be expediently erased by applying a gate voltage of −10 V in conjunction with visible light illumination for 1 s. It is found that the sub-threshold swing (SS) deteriorates slightly under light illumination, indicating that photo-ionized oxygen vacancies ( and/or ) are trapped at the interface between Al2O3 and ZTO, which assists the capture of electrons discharged from the Ni NCs charge trapping layer. The light-bias coupling action and the role of ultra-thin ZTO thickness are discussed to elucidate the efficient erasing mechanism.