Non-blocking Crossbar Research Articles

Implementations of efficient non-blocking crossbar network with novel multiplexer design in quantum-dot cellular automata

As an emerging nanotechnology, Quantum-dot Cellular Automata (QCA) has attracted extensive attentions due to its characteristics of high density, high speed, and low energy consumption. Modern high-performance System-on-Chips (SoCs) with multiple processors require interconnection networks to connect each core for improving data throughput and reducing latency, while the crossbar network is broadly used as a non-blocking interconnection architecture with high efficiency. In this paper, a method to design an efficient QCA-based N × N crossbar network utilizing optimally designed N:1 multiplexers (MUXs) is proposed, followed by a multi-layer and a single-layer implementation of its 8 × 8 design. A simplified matrix model is then introduced to provide a concise and intuitive switch control strategy, and expressions for cell count, area, latency, QCA cost, and QCA complexity of the proposed crossbar networks are derived according to the size N. Experimental results manifest that the proposed 8 × 8 crossbar networks have significant advantages on most performance parameters compared with other existing QCA-based networks.

Design and FPGA Synthesis of Three Stage Telecommunication Switching in HDL Environment

Abstract Telecommunication networks are based on crossbar switching structure. Non-blocking crossbar switching structure is used crosspoint switch fabric ICs. High performance non-blocking matrixes cross point switches are use to avoid the congested path to the output, and eliminate the bandwidth problem of one at a time. Telecommunication switching uses multistage crossbar switching to overcome the limitations of individual chips or boards. The research paper focuses on the FPGA implementation of 64 × 64 three stage telecommunication switching. The generic architecture scheme is followed to implement 64 × 64 three stage network configuration, with 64 inlets and 64 outlets as cluster size. The design is developed with the help of Xilinx ISE 14.2, software, synthesized on Virtex- 5 FPGA, and function simulation is carried out in Modelsim 10.1b student edition. Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to develop the design.

Surface-normal 4 x 4 nonblocking wavelength-selective optical crossbar interconnect using polymer-based volume holograms and substrate-guided waves

We present a 4/spl times/4 surface-normal wavelength-selective nonblocking crossbar using polymer-based volume holograms and substrate-guided waves. A prototype device is demonstrated using the center wavelengths of 750, 780, 810, and 840 nm. The employment of wavelength-division multiplexer and of address coding reduce the required 16 wavelengths to four while maintaining the 4/spl times/4 interconnects. Diffraction efficiencies of 85%, 83%, 79%, and 82% are experimentally confirmed for randomly polarized light at 750, 780, 810, and 840 mm, respectively. The measured crosstalk is less than -24 dB.

Discrete-Time Queuing Analysis of Dual-Plane ATM Switch with Synchronous Connection Control

In this paper, we propose an ATM switch with the rate more than gigabits per second to cope with future broadband service environments. The basic idea is to separate the connection control flow from the data information flow inside the switch. The proposed switch has a dual-plane switch matrix with the synchronous control algorithm. The queuing behaviors of the proposed switch are shown by the discrete-time queuing analysis. Numerical analyses are taken both in the non-blocking crossbar switch and the banyan switch with internal blocking. Results show that a proposed dual-plane 16×16 switch would have the acceptable performance with maximum throughput of about 95 percent.

Distributed control schemes for fast arbitration in large crossbar networks

In a large nonblocking crossbar switch, the controller often becomes a bottleneck in terms of both performance and reliability. We present a number of schemes for distributing the setup function among multiple controllers, thus improving both the performance and the reliability of the switch. The controllers are symmetric and operate in parallel. We present four distributed control schemes that provide a range of tradeoffs in controller complexity, speed, and hardware overhead for nonblocking operation. We derive a lower bound of N(1/spl minus/1/K) for the number of buses required for nonblocking operation of a crossbar switch with N ports and K controllers under certain constraints. We then describe a scheme that actually achieves this lower bound. Results from simulation indicate that the hardware overhead in terms of the extra buses needed is small for all the schemes if a small probability of blocking is acceptable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Self-routing crossbar packet switch employing free-space optics for chip-to-chip interconnections

A nonblocking crossbar network that employs free-space optical interconnections between optoelectronic switching nodes is proposed. The architecture can be implemented using standard electronic technologies for the switching logic, systematic self-electro-optic effect devices for modulators and detectors, and fairly simple optics to connect adjacent chips in the network. Since optical interconnections are only required between adjacent chips, this architecture may have advantages compared with other architectures that have been proposed using optical interconnections between electronic chips. In addition, a simple routing scheme is discussed that permits the optical crossbar network to be operated as a self-routing packet switch. This packet switch provides for contention resolution, priority routing, and automatic increases in the priority of blocked packets. An example illustrating one implementation of the network is then described and analyzed.

Reduction of simultaneous-switching noise in large crossbar networks

Delta-I noise (simultaneous switching noise) poses a severe limitation on the size of the individual crosspoint chips that can be used to synthesize a large crossbar network. An architectural solution for reduction of the Delta-I noise in a crossbar network by using a one-sided crosspoint switching circuits is presented. Because of the existence of multiple switching paths between any pair of terminals to be connected, these circuits provide the potential for minimizing the Delta-I noise by placing the active line drivers uniformly among the switching chips. It is shown that when the sequence of connections and disconnections is arbitrary, and with a minimal nonblocking configuration of one-sided switching chips, no algorithm exists for allocation of paths in the network that can prevent the active line drivers from getting concentrated in a few chips. However, it is possible to reduce the maximum number of active line drivers in a chip by using extra columns of chips. Tight upper bounds are achieved for the number of additional columns required for a one-sided nonblocking crossbar network when a Delta-I constraint is imposed. >