Non-binary LDPC Decoder Research Articles

Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min–Max Algorithm

Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min–Max Algorithm

Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder

Limitations on hardware resource consumption and throughput make the use of non-binary low-density parity-check (NB-LDPC) codes challenging in practical applications. This paper first proposes a novel check-node (CN) decoding algorithm called Hamming-distance trellis min-max (H-TMM) to reduce the complexity introduced by searching for two minimum values in previous TMM-based algorithms. Then, by taking advantage of the proposed algorithm and the number appearances of reliable values, a high-performance H-TMM-based NB-LDPC decoder architecture is presented. Experiments on the 32-ary (837, 726) NB-LDPC code confirmed that the proposed decoder can obtain a high throughput on less hardware resources compared with the state-of-the-art works while maintaining a competitive error-correcting performance. In particular, the proposed CN unit architecture reduced hardware resources by almost half compared to that in the latest decoder.

Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders

Nonbinary low-density parity-check (NB-LDPC) codes enable reliable data transmission over noisy channels. This article presents efficient hardware design for LDPC codes.

Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension

The Consultative Committee for Space Data Systems (CCSDS) recommends the use of short-block length Bose-Chaudhuri-Hocquenghem (BCH) and binary low-density parity-check (LDPC) codes. Despite the high error-correction capacity of non-binary low-density parity-check (NB-LDPC) codes, they have not yet been considered due to their high decoding complexity. In this paper, the feasibility of NB-LDPC coding for space telecommand link applications using a RISC-V soft-core processor plus a vector co-processor is demonstrated. The purpose of this work is to avoid the need for a dedicated decoder hardware, and thus the customized general-purpose processor which performs decoding can be reconfigured to perform other important on-board tasks. In this way, the logic utilization and power consumption can be reduced since more functionalities can be assumed by the on-board processor. The method of acceleration of a NB-LDPC decoder over GF(16) using the RISC-V vector extension is demonstrated, and a throughput of 8.48 kbps is achieved for the Forward-Backward implementation of the min-max decoding algorithm, which is compatible with the low-rate and mid-rate telecommand systems recommended by CCSDS.

High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm

Providing superior algorithm-level performance, the non-binary low-density parity-check (NB-LDPC) code is now expected to be one of the next-generation error-correction codes. However, it is hard to implement a high-throughput NB-LDPC decoder in practice due to its impractical processing complexity and the excessively long decoding time. Based on the previous extended min-sum (EMS) approach, in this work, we introduce the parallel EMS (pEMS) decoding algorithm that reduces the processing latency of each iteration by managing multiple message entries at a time. The previous two-phase node-level operation is modified to promote the proposed parallel processing without performance degradation, where the delay overheads are minimized by carefully optimizing the internal sorters with input attributes. In addition, the data accessing sequence is precisely adjusted to reduce the number of waiting cycles, further increasing the overall processing efficiency. Implemented in a 22-nm FinFET technology, as a result, the prototype two-parallel decoder for (160, 80) NB-LDPC codes operates at the speed of 950 MHz, achieving the decoding throughput of more than 7 Gb/s, which is 3.2 times faster than the state-of-the-art design.

Efficient First Four Minimum Values Finder for NB-LDPC Decoders With Compressed Messages

Trellis min-max algorithm based nonbinary low-density parity-check (NB-LDPC) decoders with compressed messages offer promising performance compared with their conventional counterparts. Recent studies have shown that reducing check-node output information to a set of four most reliable intrinsic messages strikes a balance between the hardware complexity and error-correcting performance of the decoder. Therefore, an efficient architecture to find the first four minimum values (F4M) from a given set of values is greatly required. This brief proposes an algorithm to derive F4M from two four-sorted sequences, with subsequent efficient tree structure based architecture to construct the F4M finder. To demonstrate the hardware efficiency, the proposed F4M finder architecture implementations using TSMC 90-nm CMOS technology were conducted. Experimental results confirmed that the latency of the proposed F4M finder was approximately halved compared with that of design in the state-of-the-art work. In particular, the proposed F4M finder architecture can be adopted to further improve the performance of the NB-LDPC decoders.

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.

ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.

An Improved Throughput for Non-Binary Low-Density-Parity-Check Decoder

Low-Density-Parity-Check (LDPC) based error control decoders find wide range of application in both storage and communication systems, because of the merits they possess which include high appropriateness towards parallelization and excellent performance in error correction. Field-Programmable Gate Array (FPGA) has provided a robust platform in terms of parallelism, resource allocation and excellent performing speed for implementing non-binary LDPC decoder architectures. This paper proposes, a high throughput LDPC decoder through the implementation of fully parallel architecture and a reduction in the maximum iteration limit, needed for complete error correction. A Galois field of eight was utilized alongside a non-uniform quantization scheme, resulting in fewer bits per Log Likelihood Ratio (LLR) for the implementation. Verilog Hardware Description Language (HDL) was used in the description of the non-binary error control decoder. The propose decoder attained a throughput of 10Gbps at 400-MHz clock frequency when synthesized on a ZYNQ 7000 Series FPGA.

Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes

Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction capability compared to the existing binary counterparts. However, there exist two major disadvantages in NB-LDPC decoders that they require substantial hardware resources, particularly at the check node unit (CNU), and high latency in the decoding process. In this brief, a novel minimal-set trellis min-max (MS-TMM) algorithm for NB-LDPC decoders is proposed to reduce the complexity of the CNU and enhance the decoding throughput. The decoder architecture based on the proposed MS-TMM algorithm is implemented for the (837, 726) NB-LDPC code over Galois field GF(32) using 90-nm CMOS technology. The implementation results show that the proposed architecture offers a great reduction in hardware complexity and highest efficiency compared to the state-of-the-art works. Additionally, the proposed decoder architecture is able to achieve a throughput of 1.704 Gbps and 2.254 Gbps at eight and six iterations respectively, which is a considerable improvement compared to the previous works.

GPU-based non-binary LDPC decoder with weighted bit-reliability based algorithm

In this paper, we present a graphics processing unit (GPU)-based implementation of a weighted bit-reliability based (wBRB) decoder for non-binary LDPC (NB-LDPC) codes. To achieve coalesced memory accesses, an efficient data structure for the wBRB algorithm is proposed. Based on the Single-Instruction Multiple-Threads (SIMT) programming model, a novel mapping strategy with high intra-frame parallelism is presented to improve the latency and throughput performance. Moreover, by using Single-Instruction Multiple-Data (SIMD) intrinsics, four 8-bit message elements are packed into a 32-bit unit and simultaneously processed. Experimental results show that the proposed wBRB decoder provides good tradeoff between error performance and throughput for the codes with relatively large column degrees or high rates.

Low Complexity Bit Reliability and Predication Based Symbol Value Selection Decoding Algorithms for Non-Binary LDPC Codes

The main challenge for hardware implementation of non-binary LDPC decoding is the high computational complexity and large memory requirement. To address this challenge, five new low complexity LDPC decoding algorithms are proposed in this paper. The proposed algorithms are developed specifically towards the low complexity, yet effective, decoding of the NB LDPC codes. The proposed decoding algorithms update, iteratively, the hard decision received vector to search for the valid codeword in the vector space of Galois field ${(GF)}$ . The selection criterion for least reliable symbol positions is based on the information from the failed checks and the reliability information from the Galois field structure as well as from the received channel soft information. To choose the correct value for the candidate symbol, two methods are used. The first method is based on the prediction of the error symbol from the set of Galois field symbols which maximize an objective function. In the second method, individual bits are flipped based on the reliability information obtained from the channel. Algorithms 1 and 2 flip a single symbol per iteration whilst the other three algorithms 3 , 4 and 5 flip multiple symbols in each iteration. The proposed voting based Algorithms 1 , 2 and 5 first short list the unreliable positions using a majority voting scheme and then choose the candidate symbol value from the set of the symbols in ${GF(q)}$ while not violating the field order ${q}$ . These methods simplify the decoding complexity in terms of computation and memory. Results and analysis of these algorithms show an appealing tradeoff between computational complexity and bit error rate performance for NB LDPC codes.

Design of Low-Power Non-Binary LDPC Decoder Exploiting DRAM Refresh Rate Over-Scaling

This brief presents a low-power non-binary low density parity-check decoder design exploiting domain specific information for high-throughput wireless video communication applications. The proposed technique can dynamically scale the refresh rate of DRAM according to channel conditions as well as decoding states, hence to greatly reduce the DRAM power as well as the decoder power with lower refresh overhead. Evaluation results show that the proposed technique can achieve significant decoder power saving than conventional techniques.

A 2.4-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4 $\times$ 4 256-QAM MIMO in 65-nm CMOS

Iterative detection and decoding (IDD) employs a soft-in soft-out (SISO) detector and an SISO forward error correction (FEC) decoder in an iterative loop to improve the receiver performance in multiple-input multiple-output (MIMO) wireless communications. This paper describes a 256-QAM 4 × 4 prototype IDD design made up of a minimum mean square error (MMSE) detector and a nonbinary low-density parity-check (NBLDPC) decoder with the symbol size of the NBLDPC code matched to the modulation to enhance performance. By directly translating between nonbinary symbols and constellation points, the detector-decoder interface is simplified. We present a Gb/s MMSE detector using a shortened tandem scheduling, a low-latency dual-lookup reciprocal unit, an optimized interleaved microarchitecture, and a Gb/s NBLDPC decoder with efficient internal skipping paths and memory allocation. The designs were demonstrated in a 0.7-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 1.38-Gb/s MMSE detector and a 1.7-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 1.02-Gb/s-NBLDPC decoder that are integrated in a 65-nm CMOS test chip. The chip is measured to achieve 19.2 pJ/b in detection and 20.1 pJ/b/iteration in decoding.

Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes

Non-binary low-density parity-check (NB-LDPC) codes outperform their binary counterparts in many cases. However, an NB-LDPC decoder usually requires excessive hardware resources and memory consumption. The trellis-based min-max decoding algorithm (TMMA), a well-known algorithm proposed in recent years, achieves good tradeoff between decoding performance and hardware complexity. Note that the check node processing unit (CNU) occupies the most hardware consumption. Based on the TMMA, many simplifications for the CNU have been developed with slight performance loss. The current TMMA with L truncations (L-TMMA) is promising for higher hardware efficiency than others. In this brief, based on the L-TMMA, we propose a new CNU design by incorporating algorithmic transformation and architectural optimization to further reduce the hardware complexity and thereby the critical path without any performance degradation. Synthesis results show that the proposed design achieves the lowest hardware consumption and the highest clock frequency with a small latency compared to the state-of-the-arts. Specifically, it saves more than 1/3 hardware resources compared with its original one.

An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination

This paper presents a modified Trellis Min-Max (T-MM) algorithm together with the associated architecture for non-binary (NB) low-density parity-check (LDPC) decoders. The proposed T-MM algorithm is able to reduce the memory requirements for the check-node messages through an efficient compression method and enhance the error-rate performance using the appropriate decompression. A method of updating the a posteriori log-likelihood ratio in the delta domain is used to simplify the computational and storage complexity. In order to enhance the decoding throughput, a low-complexity early termination (ET) scheme is devised by using the hard decisions of the variable-to-check messages, where, although a minor overhead is introduced, there is no visible degradation in error rate. As a proof of concept, a row-parallel layered decoder for the 32-ary (837, 726) LDPC code is implemented using a 90-nm CMOS process. The proposed decoder achieves a throughput of 1.64 Gb/s at 526.32 MHz based on eight iterations and has an area of 6.86 mm 2 . When the ET scheme is enabled, the decoder achieves a maximum throughput of 4.68 Gb/s with a frame error rate of 3.25 x 10^-6 at E_b/N_0 = 4.5 dB. The proposed NB-LDPC decoder achieves the highest throughput and hardware efficiency compared to the state-of-the-art decoders, even when the ET scheme is not enabled.

Hybrid Check Node Architectures for NB-LDPC Decoders

This paper proposes a unified framework to describe the check node architectures of non-binary low-density parity-check (NB-LDPC) decoders. Forward-backward, syndrome-based, and pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This paper is specially impacting check nodes of high degrees (or high coding rates). Results of 28-nm ASIC post-synthesis for a check node of degree 12 (i.e., a code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared with the classical forward-backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256), and these preliminary results open the road to high decoding throughput, high rate, and high-order Galois field NB-LDPC decoder with a reasonable hardware complexity.

A 2.267-Gb/s, 93.7-pJ/bit Non-Binary LDPC Decoder With Logarithmic Quantization and Dual-Decoding Algorithm Scheme for Storage Applications

Non-binary low-density parity-check (NB-LDPC) codes are a promising class of error-correcting codes that provide excellent coding gain beyond that of their binary counterparts. However, their decoding complexity has thus far limited practicality. We present an NB-LDPC decoder with information throughput of 2.267 Gb/s and power consumption of 212.4 mW, yielding an energy efficiency of 93.7 pJ/bit, implemented in 40-nm CMOS technology. The employed code is long and high-rate without degree-2 variable nodes, resulting in a low error floor and making the code appropriate for storage applications. A logarithmic quantization scheme is proposed to enable aggressive wordlength reduction to alleviate hardware complexity. In addition, a dual-decoding algorithm scheme is employed to alleviate the computational complexity of decoding, realized in an efficient architecture with high parallelism and avoidance of idle clock cycles.

Basic-Set Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields

Nonbinary low-density parity-check (NB-LDPC) codes outperform their binary counterparts in terms of error-correction performance. However, the drawback of NB-LDPC decoders is high complexity, especially for the check node unit (CNU), and the complexity increases considerably when increasing the Galois-field (GF) order. In this paper, a novel basic-set trellis min–max algorithm is proposed to greatly reduce not only the CNU complexity but also the number of messages exchanged between the check node and the variable node compared with previous studies, which is highly efficient for higher order GFs. In addition, the proposed CNU is designed to compute the messages in a parallel way. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) and the (1512, 1323) code over GF(64) using 90-nm CMOS technology, and obtained a reduction in the complexity by 30% and 37% for the CNU, and 40% and 37.4% for the whole decoder, respectively. Moreover, the proposed decoder achieves a higher throughput at 1.67 Gbit/s and 1.4 Gbit/s compared with the other state-of-the-art high-rate NB-LDPC decoders with high-order GFs.

A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications

Compared to binary Low-Density Parity-Check (LDPC) codes, nonbinary LDPC (NB-LDPC) codes have better error correction performance under short-to-moderate block lengths or high-order modulations. Traditional min-sum-based soft decoding algorithms for NB-LDPC codes suffer from large computational complexity, which leads to inefficient hardware implementations. The Multiple-symbol-reliability weighted Bit-Reliability-Based (MwBRB) hard decoding algorithm achieves a good tradeoff between error correction performance and decoding complexity. However, efficient hardware implementations based on the MwBRB algorithm have not been investigated. In this brief, an improved layered MwBRB algorithm is first proposed, which results in faster convergence rate than the MwBRB algorithm. Then, an ultra-high-throughput low-complexity decoder architecture with an efficient partially parallel processing schedule is also presented. Finally, the proposed architecture is coded with RTL and synthesized under the TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed decoder for a (837, 726) quasi-cyclic NB-LDPC code over GF(25) achieves a throughput of 21.66 Gbps and an area efficiency of 4.77 Gbps/M-gates under the TSMC 90-nm CMOS technology. The proposed decoder reaches a throughput more than 20 Gbps for the first time among the prior NB-LDPC decoders, and the area efficiency is far beyond the state-of-the-art designs.