Field-effect Transistor Nonvolatile Memory Research Articles

Non-volatile memory field effect transistor composed of ferroelectric Mn-doped InP thin films and single-layer MoS2 channel

Ferroelectric properties can be generated by doping semiconductor thin films of ZnO and InP with a transition metal such as Mn. Furthermore, ferroelectric thin films exhibiting ferroelectric properties can be utilized as non-volatile memory components, potentially replacing conventional flash memory. In this study, we investigated non-volatile memory properties using field-effect transistors (NVMFET) fabricated from Mn-doped InP (MIP) thin films and single-layer MoS2 sheets. The 5 % Mn-doped MIP thin films exhibited a larger remanent polarization of 8.2 μC/cm2 compared to the 3 % Mn-doped films with 5.1 μC/cm2. The NVMFET devices, operating as non-volatile memory devices, demonstrated a distinct memory window for current changes. Notably, enhancing the remanent polarization of the 5 % Mn-doped MIP thin film further improved the memory window of the corresponding NVMFET.

A flexible floating-gate based organic field-effect transistor non-volatile memory based on F8BT/PMMA integrated floating-gate/tunneling layer

The solution mixing method was adopted to build polymer semiconductor poly(9,9-dioctylflfluorene-co-benzothiadiazole) (F8BT) nanoparticles (NPs), which were mixed with poly (methyl methacrylate) (PMMA) in a solution to prepare an integrated floating-gate/tunneling layer. On this basis, flexible floating-gate based organic field-effect transistor non-volatile memories (F-OFET-NVMs) were prepared. The intrinsic correlations of the microstructures in the integrated floating-gate/tunneling layer of the memory devices with the device performance were explored. Moreover, correlations of the charge injection and discharge, physical mechanism of memory, and charge trapping capacity of the floating-gate/tunneling layer with different F8BT/PMMA mass ratios with the key parameters of memory devices were investigated. Relevant results indicate that the memory devices are able to well trap charges inside the F8BT NPs during operation at a programming voltage of +40 V, an erasing voltage of −40 V, and a pulse width of 1 s. The floating gate acquires the injected and trapped bipolar charges (electrons and holes). The optimized high-performance memory device is found to have an average memory window of 9.5 V, remain stable for more than three years, and have reliable stability in more than 100 erase/write cycles. Furthermore, the memory device also exhibits outstanding durability under mechanical bending and still has high storage stability after 6,000 times of bending with a bending radius of 3 mm. The research results powerfully promote the research progress of applying semiconductor polymers to memory devices.

High-performance flexible pentacene transistor memory with PTCDI-C13 as N-type buffer layer

Flexible organic field-effect transistor nonvolatile memories (OFET-NVMs) with polymer electrets have aroused great attention for its important role in next-generation flexible data storage devices application. However, the OFET-NVMs to date still hardly reach the requirements for practical applications. In air environment, the positively charged defects formed in pentacene near the interface with polymer, result in unsatisfied high programming/erasing (P/E) voltages. Here, we propose an OFET memory structure, in which an n-type semiconductor N, N′-Bis(3-pentyl) perylene-3, 4, 9, 10-bis(dicarboximide) (PTCDI-C13) is inserted between pentacene and poly(4-vinyl phenol. Based on the electrostatic induction effect, electrons are induced on the surface of PTCDI-C13 due to the electrostatic field generated by the positive charges at the interface of pentacene/polymer, and compensate part of the positive charges at the interface, resulting in the reduction of the height of hole-barrier. The flexible memory device with PTCDI-C13 exhibits a memory window of larger than 7 V at P/E voltages (±20 V), fast switching speeds (0.5 ms), good P/E endurance (>400 cycles), large field-effect mobility (0.026 cm2 V−1 s−1), and long retention time (over 104 s).

Comparison of 2-D MoS2 and Si Ferroelectric FET Nonvolatile Memories Considering the Trapped-Charge-Induced Variability

This brief investigates scaled 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) considering the trapped-charge-induced variability with the aid of Technology Computer Aided Design (TCAD) atomistic simulations. Our study indicates that, compared with the Si channel, the monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> channel with larger electron affinity and bandgap energy can result in an FeFET NVM with larger memory window (MW). Moreover, due to its lower channel permittivity and channel thickness, the 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FeFET possesses a superior immunity to trapped-charge-induced variability, and the gap in MW between MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and Si FeFETs enlarges under the presence of trapped charges. Besides, due to its atomically thin channel thickness and superior electrostatic integrity, the scaled 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FeFET possesses a remarkably better read margin than the Si counterpart. Our study may provide insights for future scaling of FeFET NVMs.

Improving the Scalability of Ferroelectric FET Nonvolatile Memories With High-k Spacers

This paper investigates scaled ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) with high-k spacer device design considering ferroelectric-dielectric random phase variations with TCAD atomistic simulations. Our study indicates that, in addition to raising the orthorhombic phase and reducing the grain size of the ferroelectric, using high-k spacers can serve as another way to enhance the scalability of FeFETs because it improves both the mean memory window (MW) and the worst-case MW. More importantly, these improvements increase with the down-scaling of gate length. In addition, we have investigated the impact of high-k spacers on the critical electric field across interfacial layer (EIL) for the reliability of FeFET NVMs. Our study suggests that, for scaled FeFETs with high-k spacers, the highest EIL during write operation is no longer located near the S/D edge but at the mid channel. Using high-k spacers can reduce the mid-channel EIL, and the reduction increases with decreasing gate length due to the increasing impact of high-k spacers. Our study may provide insights for future high-density FeFET design.

UV-Enabled Multibit Organic Transistor Memory With High Controllability and Stability

An organic field-effect transistor nonvolatile memory with multibit storage capability and selective UV response was demonstrated, which showed good retention for all the memory states. The programming/erasing of the device operating at a low voltage was enabled by solar-blind UV light of 254 nm, and it had no response to 365 nm UV light and visible light. The stepwise switching between the memory states was controlled only by the number of the programming/erasing pulses, rather than by programming/erasing voltage or duration. The multibit memory feature is ascribed to the cumulative and reversible charge trapping in the employed polymer electret layer, and this architecture may offer a promising approach to multibit organic-based memories.

A three-bit-per-cell via-type resistive random access memory gated metal-oxide semiconductor field-effect transistor non-volatile memory with the FORMing-free characteristic

We present an embedded memory for possible neuromorphic computing applications using a via-type resistive random access memory (RRAM) gated metal-oxide semiconductor field-effect transistor (MOSFET). By this arrangement, the threshold voltage (V th) of the MOSFET is modulated by the resistance of the via-type RRAM. When the resistance of the via-type RRAM is in a high-resistance state (HRS), the word-line voltage (V WL) is consumed mostly across the via-type RRAM and little is left on the gate dielectric layer of the MOSFET; the V th of the MOSFET is boosted. In contrast, when the resistance of the via-type RRAM is in a low-resistance state (LRS), with the resistance value much smaller than that of the gate dielectric of the MOSFET, the VWL will be dropped majorly on the gate dielectric of the MOSFET, and the V th of the MOSFET will be much reduced than that of the MOSFET gated by the via-type RRAM in a HRS. The experimental results show that, in a direct-current mode, the memory window achieves 1 V between a LRS and a HRS of the via-type RRAM gated MOSFET. In an alternating current mode, the LRS can be SET at 10 nanoseconds; the HRS can be RESET at 5 nanoseconds. Furthermore, three-bit-per-cell operation of the via-type RRAM gated MOSFET is demonstrated. The eight conductance states are distributed evenly between 100 micro- and 100 picosiemens with almost isometric gaps in between. The endurance tests were executed for eight conductance states with one million cycles for four pairs. Finally, the retention tests of eight states were kept under 125 °C for one month.

High-Mobility, Low-Voltage Programmable/Erasable Ferroelectric Polymer Transistor Nonvolatile Memory Based on a P(VDF-TrFE)/PMMA Bilayer Gate Insulator

Low mobility and high operating voltages are bottlenecks in the practical application of ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memory (NVM). In this article, we demonstrate a high-mobility polymer semiconductor-based Fe-OFET NVM that can well operate at low programming/erasing voltages ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> /V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> ). The issue that hinders the reduction of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> /V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> in Fe-OFET NVMs is discussed. We develop a route to resolve the issue by building a thin bilayer gate insulator consisted of an ultrathin poly(methyl methacrylate) (PMMA) and a thin poly(vinylidenefluoride-trifluoroethylene) films. The processing compatibility, that is, the tri-layered core architecture consisting of polymer semiconductor and insulator films is prepared by a full-solution technology, is confirmed. The mechanism of the performance improvements by using the ultrathin PMMA in the Fe-OFET NVMs is investigated. As a result, the Fe-OFET NVM exhibits excellent performances at low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> /V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> of ±15 V, with a high mobility up to 1.75 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, reliable memory endurance over 400 cycles, and stable memory retention over 65000 s.

Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories

This article investigates the impact of interface trapped-charge variations on the dimensional scaling of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) under two scenarios: a uniform ferroelectric and random ferroelectric-dielectric (FE-DE) phase distribution. Our study indicates that both memory window (MW) and read margin decrease with increasing trap density ( ), and the MW of FeFET devices with scaled channel width can be more vulnerable to the trapped-charge variations than that with scaled gate length. Under the presence of the FE-DE phase variation, for low , the impact of trapped charges is mainly on the MW degradation for the high MW instances. As the continues to rise, the trapped charges can further worsen the worst case MW significantly. Besides, when down-scaling the interfacial layer thickness of the FeFET device to increase the MW, the increased σMW due to the random interface trapped charges may also need to be considered. Our study may provide insights for device design with advanced FeFET NVMs.

High-performance polymer semiconductor-based ferroelectric transistor nonvolatile memory with a self-organized ferroelectric/dielectric gate insulator

Ferroelectric organic field-effect transistor nonvolatile memories (Fe-OFET-NVMs) offer attractive features for future memory applications, such as flexible and wearable electronics. Polymer semiconductor-based top-gate Fe-OFET-NVMs possess natural advantages in the device structure and processing manufacturing, compared to small-molecule semiconductor-based bottom-gate Fe-OFET-NVMs. However, their performances, such as mobility and operating voltages, should be further improved to be comparable to those of the latter. In this Letter, we develop a route to achieve high-performance top-gate Fe-OFET-NVMs, by employing a polymer semiconductor channel and self-organized ferroelectric/dielectric gate insulators, which were processed by a solution spin-coating technique. The optimal Fe-OFET-NVM exhibits a high mobility of 1.96 cm2/V s on average, a reliable endurance over 400 cycles, a stable retention capability over 6 × 104 s, and a life more than one year. Furthermore, the operating voltage of the Fe-OFET-NVM is reduced to ±20 V by scaling down the thickness of the ferroelectric/dielectric gate insulator. The whole performances of our memories are comparable to or better than those of the previous Fe-OFET-NVMs.

Depletion induced depolarization field in Hf1−xZrxO2 metal-ferroelectric-semiconductor capacitors on germanium

Germanium Metal-Ferroelectric-Semiconductor (MFS) capacitors based on ferroelectric Hf1−xZrxO2 (HZO) with clean, oxide free Ge/HZO interfaces emerge as an interesting layer structure for the fabrication of ferroelectric field effect transistor (FeFET) non-volatile memory devices. It is shown that, at low temperature (&amp;lt;160 K), a semiconductor depletion forms in Ge near the interface, resulting in an increase in coercive voltage by about 2 V, accompanied by a distortion of the ferroelectric hysteresis with subloop asymmetric behavior, which becomes more severe at higher frequencies of measurement. At higher temperatures, the Ge surface near the ferroelectric is easily inverted due to the low energy gap of Ge, providing sufficient screening of the polarization charge by minority free carriers, in which case, nearly ideal, symmetric hysteresis curves are recovered. The depolarization field is experimentally extracted from the coercive voltage and the capacitance measurements, is found to be ∼ 2.2 MV/cm in the low temperature range, comparable to the coercive field, then rapidly decreases at higher temperatures, and effectively diminishes at room temperature. This makes Ge MFSs good candidates for FeFETs for low voltage non-volatile memory with improved reliability.

Organic Transistor Nonvolatile Memory with Three-Level Information Storage and Optical Detection Functions.

By the current processing technology, it is a challenge to obtain ultrahigh-density information storage in the conventional binary floating-gate-based organic field-effect transistor (FG-OFET) nonvolatile memories (NVMs). To develop a multilevel memory in one cell is a feasible solution. In this work, we demonstrate FG-OFET NVMs with an integrated polymer floating-gate/tunneling (I-FG/T) layer consisting of poly(9,9-dioctylfluorene-co-benzothiadiazole) (F8BT) and polystyrene. The photoelectric effect of organic/polymer semiconductors is used to improve the controllability of the polarity and the number of the charges stored in the floating-gate. The FG-OFET NVMs integrate light sensitivity and nonvolatile information storage functions. By selecting suitable optical and electrical programming/erasing conditions, three-level information storage states, corresponding to electron storage, approximate neutrality, and hole storage in the floating-gate, are achieved and freely switched to each other. The memory mechanism and the dependence of the memory performances on the F8BT contents in I-FG/T layers are investigated. As a result, good memory performances, with mobility larger than 1.0 cm2 V-1 s-1, reliable three-level switching endurance over 100 cycles, and stable three-level retention capability over 20 000 s, are achieved in our memory. Furthermore, an imaging system with a nonvolatile information storage function is demonstrated in a 16 × 5 array of FG-OFET NVMs.

Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution

This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.

Characteristics of MoS2 monolayer non-volatile memory field effect transistors affected by the ferroelectric properties of BiFeO3 thin films with Pt and SrRuO3 bottom electrodes grown on glass substrates

We investigated the characteristics of ferroelectric non-volatile random-access memory field effect transistors (MoS2-BFO NVRAM FETs) consisting of monolayer MoS2 channels, BiFeO3 (BFO) gate layers, and Pt and SrRuO3 bottom electrodes on glass substrates. As a result of the comparative experiments of the Pt and SrRuO3 bottom electrodes, it was confirmed that the BFO gate layer using the SrRuO3 bottom electrode showed a higher remanent polarization, faster switching time, and superior fatigue endurance than the BFO gate layer using the Pt bottom electrode. It is suggested that the good ferroelectric properties of the BFO gate dielectric layer on the SrRuO3 bottom electrode is resulting from its (001)-oriented growth. The MoS2 BFO NVRAM FET with a SrRuO3 bottom electrode exhibited a wider memory window than the Pt bottom electrode because the SrRuO3 bottom electrode had a higher remanent polarization of the BFO gate layer compared to the Pt bottom electrode.

Organic transistor nonvolatile memory with an integrated molecular floating-gate/tunneling layer

Floating-gate based organic field-effect transistor (FG-OFET) nonvolatile memories (NVMs) are demonstrated based on an integrated molecular floating-gate/tunneling layer, in which small molecular fullerene (C60) acting as the floating-gate and long-chain alkane molecule tetratetracontane acting as the tunneling layer are synchronously prepared by vacuum thermal evaporation. The effects of the thickness and the component of the integrated floating-gate/tunneling layer on the performances of memory are investigated. As a result, a high performance FG-OFET NVM is achieved, with a large memory window of 8.0 V on average, stable retention capability over 10 years, and reliable switching endurance over 100 cycles at the programming/erasing voltages of ±40 V, at an optimized condition.

Low-voltage programmable/erasable high performance flexible organic transistor nonvolatile memory based on a tetratetracontane passivated ferroelectric terpolymer

Abstract Future flexible electronic systems require memory devices combining low power consumption and mechanical bendability. However, high programming/erasing (P/E) voltages, which are universally required to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a novel route to achieve a low-voltage programmable/erasable flexible Fe-OFET NVM. Ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)], rather than the conventional ferroelectric copolymer poly(vinylidene-fluoride-trifluoroethylene) [P(VDF-TrFE)], is used as the gate dielectric. The low coercive field of P(VDF-TrFE-CTFE) is the main contribution to the low-voltage operation in the Fe-OFET NVM, even with a relative thick ferroelectric gate dielectric layer. By depositing a long-chain alkane molecule Tetratetracontane (TTC) as the passivation layer on the surface of P(VDF-TrFE-CTFE) film, the layer-by-layer growth mode of semiconductor pentacene is obtained, which results in a large crystalline grain and good interface morphology at the channel/dielectric. Therefore, the mobility of Fe-OFET NVMs is greatly improved. As a result, a high performance flexible Fe-OFET NVM is achieved, with a low P/E voltage of ±15 V, high mobility up to 0.5 cm2 V−1 s−1, reliable P/E endurance property over 1000 cycles, stable data storage retention capability over 6000 s, and excellent mechanical bending durability without visible degradation after 2000 repetitive tensile bending cycles at a small curvature radius of 4.0 mm.

High Mobility Flexible Ferroelectric Organic Transistor Nonvolatile Memory With an Ultrathin ${\text {AlO}}_{{X}}$ Interfacial Layer

The low mobility is a primary issue to prevent the practical application of the ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memory (NVM). In this paper, we propose a route to resolve this issue by inserting an ultrathin ${\text {AlO}}_{X}$ layer between the semiconductor film and the ferroelectric polymer film. A high mobility of 6.5 $\text{cm}^{2}\cdot \text {V}^{-1}\cdot \text {s}^{-1}$ is achieved in the fabricated flexible Fe-OFET NVM, which also exhibits good memory performances with a large memory window of 17.2 V, a high memory on-off ratio up to $2 \times 10^{5}$ , reliable switching endurance property over 600 cycles, and stable retention capability with the memory on-off ratio larger than 102 over 104 s, at the low programming/erasing voltages of ±15 V.

Solution Processed Organic Transistor Nonvolatile Memory With a Floating-Gate of Carbon Nanotubes

In this letter, an organic field-effect transistor nonvolatile memory (NVM), based on single-walled carbon nanotubes (SWNTs) as a nano floating-gate, is demonstrated, for which a four-layer stacked core architecture was processed by following the sequential solution spin-coating method. The SWNTs, separated by spin-coating, are distributed in the matrix of copolymer poly (styrene-block-paraphenylene) to act as the charge trapping sites. The memory of the floating-gate organic transistor so prepared exhibits excellent NVM characteristics,with a large memory window of 26.7 V, memory on/off ratio larger than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , stable charge storage retention capability for over 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s with a memory on/off ratio over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the reliable memory endurance property of over 500 Hz.

Low-voltage operating flexible ferroelectric organic field-effect transistor nonvolatile memory with a vertical phase separation P(VDF-TrFE-CTFE)/PS dielectric

Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. However, high programming/erasing voltages, which are universally needed to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a route to achieve a low-voltage operating flexible Fe-OFET NVM. Utilizing vertical phase separation, an ultrathin self-organized poly(styrene) (PS) buffering layer covers the surface of the ferroelectric polymer layer by one-step spin-coating from their blending solution. The ferroelectric polymer with a low coercive field contributes to low-voltage operation in the Fe-OFET NVM. The polymer PS contributes to the improvement of mobility, attributing to screening the charge scattering and decreasing the surface roughness. As a result, a high performance flexible Fe-OFET NVM is achieved at the low P/E voltages of ±10 V, with a mobility larger than 0.2 cm2 V−1 s−1, a reliable P/E endurance over 150 cycles, stable data storage retention capability over 104 s, and excellent mechanical bending durability with a slight performance degradation after 1000 repetitive tensile bending cycles at a curvature radius of 5.5 mm.

Excellent low-voltage operating flexible ferroelectric organic transistor nonvolatile memory with a sandwiching ultrathin ferroelectric film

The high operating voltage is a primary issue preventing the commercial application of the ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memory (NVM). In this work, we propose a novel route to resolve this issue by employing two ultrathin AlOX interfacial layers sandwiching an ultrathin ferroelectric polymer film with a low coercive field, in the fabricated flexible Fe-OFET NVM. The operation voltage of Fe-OFET NVMs decreases with the downscaling thickness of the ferroelectric film. By inserting two ultrathin AlOX interfacial layers at both sides of the ultrathin ferroelectric film, not only the gate leakage is prominently depressed but also the mobility is greatly improved. Excellent memory performances, with large mobility of 1.7 ~ 3.3 cm2 V−1 s−1, high reliable memory switching endurance over 2700 cycles, high stable data storage retention capability over 8 × 104 s with memory on-off ratio larger than 102, are achieved at the low operating voltage of 4 V, which is the lowest value reported to data for all Fe-OFET NVMs. Simultaneously, outstanding mechanical fatigue property with the memory performances maintaining well over 7500 bending cycles at a bending radius of 5.5 mm is also achieved in our flexible FE-OFET NVM.