Nonvolatile Memory Cell Research Articles

A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory

Nonvolatile memory (NVM) technologies are promising candidates as the next-generation main memory due to high scalability and low energy consumption. However, the performance bottlenecks, such as high write latency and low cell endurance, still exist in NVMs. To address these problems, frequent pattern compression schemes have been widely used, which however suffer from the lack of flexibility and adaptability. In order to overcome these shortcomings, we propose a well-adaptive NVM write scheme, called dynamic frequent pattern compression (DFPC), to significantly reduce the amount of write units and extend the lifetime. Instead of only using static frequent patterns in existing FPC schemes, which are predefined and not always efficient for all applications, the idea behind DFPC is to exploit the characteristics of data distribution in execution to obtain dynamic patterns, which often appear in the real-world applications. To further improve the compression ratio, we exploit the value locality in a cache line to extend the granularity of dynamic patterns. Hence, DFPC can encode the contents of cache lines with more kinds of frequent data patterns. Moreover, to further support efficient write and read operations in the context of multilevel/triple-level cell NVMs, we need to extend the DFPC to improve performance in terms of the access latency and energy consumption. We hence propose a latency-optimized and energy-efficient compression write scheme to encode the compressed data with low energy and latency states, i.e., enhanced DFPC, thus reducing the latency and energy consumption. We implement DFPC in GEM5 with NVMain and execute the applications from SPEC CPU2006 to evaluate our scheme. Experimental results demonstrate the efficacy and efficiency of DFPC. We have released the source codes for public use at Github https://github.com/dfpcscheme/DFPCScheme .

Monolayer MoS2-based nonvolatile transistors with a titanium nitride in the gate

Low-power, nonvolatile transistors are demanded in the digital electronics development. In our work, molybdenum disulfide (MoS2) acts as the channel material integrated with TiN, which is used as a floating gate to build a floating gate transistor. Our transistor exhibits a large hysteresis of 4 V (Vd = 0.1 V), high on/off ratio of 105, and symmetry writing and erase voltage. The excellent device characteristics such as nondestructive data readout, low operation voltage, and wide memory window inherent in single-layer MoS2 show their great potential to be applied in nonvolatile memory cells.

Nonvolatile Spintronic Memory Cells for Neural Networks

A new spintronic nonvolatile memory cell analogous to 1T DRAM with non-destructive READ is proposed. The cells can be used as neural computing units. A dual-circuit neural network architecture is proposed to leverage these devices against the complex operations involved in convolutional networks. Simulations based on HSPICE and MATLAB were performed to study the performance of this architecture when classifying images as well as the effect of varying the size and stability of the nanomagnets. The spintronic cells outperform a purely charge-based implementation of the same network, consuming $\approx ~100$ -pJ total energy per image processed.

Electromigration-induced resistance switching in indented Al microstrips

Non-volatile resistive memory cells are promising candidates to tremendously impact the further development of Boolean and neuromorphic computing. In particular, nanoscale memory-bit cells based on electromigration (EM)-induced resistive switching in monolithic metallic structures have been identified as an appealing and competitive alternative to achieve ultrahigh density while keeping straightforward manufacturing processes. In this work, we investigate the EM-induced resistance switching in indented Al microstrips. In order to guarantee a large switching endurance, we limited the on-to-off ratio to a minimum readable value. Two switching protocols were tested, (i) a variable current pulse amplitude adjusted to ensure a precise change of resistance, and (ii) a fixed current pulse amplitude. Both approaches exhibit an initial training period where the mean value of the device’s resistance drifts in time, followed by a more stable behavior. Electron microscopy imaging of the devices show irreversible changes of the material properties from the early stages of the switching process. High and low resistance states show retention times of days and endurances of ∼103 switching cycles.

Plasmonic nanogap enhanced phase-change devices with dual electrical-optical functionality.

Modern-day computers rely on electrical signaling for the processing and storage of data, which is bandwidth-limited and power hungry. This fact has long been realized in the communications field, where optical signaling is the norm. However, exploiting optical signaling in computing will require new on-chip devices that work seamlessly in both electrical and optical domains, without the need for repeated electrical-to-optical conversion. Phase-change devices can, in principle, provide such dual electrical-optical operation, but assimilating both functionalities into a single device has so far proved elusive owing to conflicting requirements of size-limited electrical switching and diffraction-limited optical response. Here, we combine plasmonics, photonics, and electronics to deliver an integrated phase-change memory cell that can be electrically or optically switched between binary or multilevel states. Crucially, this device can also be simultaneously read out both optically and electrically, offering a new strategy for merging computing and communications technologies.

Memristive Phase Change Memory

The paper presents study on and simulation of resistive nonvolatile phase change memory (PCM) cell in NG Spice programming environment. The chalcogenide alloy based PCM cell model demonstrates switching between amorphous and crystalline phases. The crystalline factor, responsible for the phase change process, is programmed by applied variable electrical pulse. Parameters phase change, range of operating temperature, the crystalline factor are mapped and presented.

Investigation of Multi-Level Cell Characteristic in Amorphous Indium-Gallium-Zinc Oxide Thin-Film-Transistor Based 1T-1R Non-Volatile Memory Device.

In this work, we have implemented nonvolatile resistive random access memory (ReRAM) cells consisting of one transistor (1T) and one resistor (1R) configuration by integrating a high-performance InGaZnO (IGZO) thin-film-transistor (TFT) and an HfO₂ resistive switching component on a single substrate for system-on-panel (SoP) technology. ReRAM cells with a 1T-1R configuration can reduce undesired crosstalk caused by leakage current between adjacent memory cells. The a-IGZO TFTs used for 1T-1R integration showed excellent electrical characteristics with a high field-effect mobility of 10.8 cm²/V s, a low subthreshold swing of 226 mV/dec and a large on-off current ratio of 9.2 × 107. The 1T-1R integrated memory cells exhibited BRS behavior, uniform distribution of resistance states and operating voltage, stable DC endurance and reliable data retention characteristics. In addition, we obtained MLC characteristics in a 1T-1R integrated memory cell by controlling the driving current with the gate voltage of a-IGZO TFTs. In multi-level operation, it showed a low operating voltage of 1 V, stable endurance and reliable retention characteristics at 85 °C.

Theoretical study of ferroelectric-gated nanoelectromechanical diode nonvolatile memory cell

Based on the polarization property and negative-capacitance (NC) effect of ferroelectric capacitors, nanoelectromechanical (NEM) diode nonvolatile memory cells (NC-NEM diode NVMs) are proposed for use in random-access memory arrays. It is observed that, by optimizing the structural parameters of the NEM memories, the NC-NEM diode NVMs can achieve more scaled program/erase voltages and better switching delays, when compared to the existing NEM diode memories. Moreover, the NC-NEM diode NVM has a one-directional current path, which is desirable in random-access memory arrays to block the sneak leakage.

Improving the Lifetime of Non-Volatile Cache by Write Restriction

The attractive features such as low static power and high density exhibited by the Non-Volatile Memory (NVM) technologies makes them a promising candidate in the memory hierarchy, including caches. However, the limited write endurance with the write variations governed by the access patterns and the applied replacement policies reduce the chance of NVMs as a successor of SRAM. These write variations are of concern as they not only breakdown the NVM cells but also reduce the effective lifetime. This paper proposes efficient techniques to mitigate the intra-set write variation to improve the lifetime of the NVM cache. Our first two techniques partition the cache into windows of equal size and distribute the writes uniformly across the cache set by employing the window as write-restricted or read-only. The selection of the window in these techniques is by rotation or with the help of counters. In our third technique, different cache ways are employed as a write-restricted over the period of execution to distribute the writes uniformly. Experimental results using full system simulation show the significant reduction in intra-set write variation along with improvement in the cache lifetime.

Resistive Switching Effect with ON/OFF Current Relation up to 109 in 2D Printed Composite Films of Fluorinated Graphene with V2O5 Nanoparticles

AbstractComposite films consisting of fluorinated graphene flakes with vanadium oxide (V2O5) nanoparticles exhibit a stable bipolar resistive switching effect that depends on the size of the composite particles, on the proportion between the film components, on the heat‐treatment conditions of the films (or on the hydration degree of V2O5 nanoparticles), and on the area of the structures. The ON/OFF current ratio of printed crossbar structures reaches 106–109 for films 20–50 nm thick, with the switching voltage varying in the range from 1.5 to 3.7 V, 30 ns time for structure switching, and endurance characteristics up to 1.3 × 103 switching cycles without any changes in ON/OFF current ratio. A mechanism to describe the resistive switching effect implying the formation of sign‐alternating electric fields in a multibarrier structure is proposed. The investigated structures are of interest for the fabrication of nonvolatile memory cells, including memory cells for flexible and printed electronics.

Design of Magnetic Non-Volatile TCAM With Priority-Decision in Memory Technology for High Speed, Low Power, and High Reliability

Recently, various magnetic non-volatile ternary content-addressable memory (MNV-TCAM) cells that use magnetic tunnel junctions (MTJs) as storage units have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption for search operation. In addition, the restrictions on the ordering of the TCAM array required by the using of the priority encoder to resolve the multiple match problem due to the `X' results in large delay and high energy consumption for update operation. To address these issues, the novel MNV-TCAM cell is first proposed, aiming to achieve high-speed, low-power, and high-reliable search operation. In addition to the search data operation, it can realize a search length operation. By exploiting this search length operation, we then present circuit-level design of the MNV-TCAM with a priority-decision in memory technology, which can utilize the length information of matched words sorted in an arbitrary order to decide the highest-priority matched word by performing a three-phase search operation. It implies that the restrictions on the ordering can be eliminated, thus, improving the update speed and energy-efficiency. Finally, hybrid CMOS/MTJ simulations are performed to demonstrate its functionality and evaluate its performance in terms of search reliability, search speed, and search energy consumption.

Layer‐Switching Mechanisms in Sb2Te3

Interfacial phase‐change memory (iPCM) based on layer‐structured Ge‐Sb‐Te crystals has been recently proposed, offering an energy‐efficient implementation of nonvolatile memory cells and supplementing the development of Ge‐Sb‐Te‐based phase‐change random access memories (PRAMs). Although the working principle of iPCM is still under debate, it is believed that layer‐switching plays a role in the switching process between the low‐resistance and high‐resistance states of iPCM memory cells. However, the role of Ge in forming swapped bilayers—the key elements for layer‐switching—is not yet clarified. This work manages to achieve layer‐switching in Sb2Te3 thin films by manipulating the formation of bilayer defects using magnetron sputtering and post‐thermal annealing. By combining scanning transmission electron microscopy (STEM) experiments with density functional theory (DFT) calculations, the essential role of Sb‐Te intermixing is elucidated in stabilizing swapped bilayers at a low energy cost. In situ STEM experiments provide a real‐time and real‐space view of dynamical reconfiguration of van der Waals‐like gaps in Sb2Te3 thin films under electron‐beam irradiation. The results show that the Ge atoms are not necessary for the formation and motion of swapped bilayers, providing atomic insights on the layer‐switching mechanism in layer‐structured binary and ternary group V‐ and IV–V‐tellurides for memory applications.

New multi-bit non-volatile memory cells with higher data storage density

Researchers demonstrate proof-of-concept of an easy to fabricate MRAM architecture with multi-bit cells driven by a single transistor.

Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin

Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin

Design and development of memristor‐based RRAM

A power- and variability-aware non-volatile resistive random access memory (RRAM) cell is presented. Non-volatility is achieved due to the use of a memristor as a memory element, which when integrated with a carbon nanotube field-effect transistor (CNFET) helps achieve tremendous robustness against process variation. The half-select issue, inherent in the 2T2M RRAM cell (state-of-the-art design based on the memristor) have been resolved and its circuit parameters have been compared with those of the proposed cell. Also, the proposed cell has been compared with the standard 6T SRAM (S6T) cell. The proposed cell shows 1.6×/4.08× narrower read delay/write delay variability compared with 2T2M. 5CNFET2M also shows 1.8× narrower read delay variability than that of S6T. Furthermore, the proposed cell shows 6.9× shorter write delay in comparison with the 2T2M RRAM cell. 5CNFET2M consumes 10 6 ×/1.34× lower power during hold mode compared with the conventional 6T static random access memory/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared with both the cells. All the simulated data, presented here are at the nominal supply voltage of 1 V. These improvements are gained at the expense of slightly longer read time compared with 2T2M/S6T and 31.3× longer write delay compared with S6T.

Resistive switching effects in fluorinated graphene films with graphene quantum dots enhanced by polyvinyl alcohol

Two-layer films of partially fluorinated graphene (PFG) with graphene quantum dots and polyvinyl alcohol (PVA) were prepared by means of 2D printing technology. A stable resistive switching effect with the ON/OFF current ratio amounting from one to 4–5 orders of magnitude is found. The decrease in the PVA thickness leads to a change of the unipolar threshold switchings to the bipolar resistive switchings. The crossbar Ag/PFG/PVA/Ag structures retain their performance up to 6.5% deformation. The switching phenomenon is observed for a period about a year. The traps with characteristic activation energies ∼0.05 eV are suggested to be responsible for resistive switching. The time of charge-carrier emission from the localized states was found to be ∼5 μs. A quality model to describe the resistive switching effect in two-layer films implying the conduction over quantum dots proceeding with the participation of active traps at the PFG/PVA interface is proposed. The structures with the design demonstrated threshold resistive switching have their high potential for development of selector devices integrated to sensor or memristors circuits, for information storage and data processing, for flexible and wearable electronics. The structures with lower PVA thickness and the bipolar threshold switching are perspective for non-volatile memory cells for printed and flexible electronics.

A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for High-Speed, Low-Power, and High-Reliable Search Operation

Recently, several magnetic tunnel junction (MTJ)-based non-volatile ternary content-addressable memory (NV-TCAM) cells have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption during search operations. To address these issues, we propose a novel MTJ-based NV-TCAM cell, which is composed of 15 transistors and 4 MTJs (15T-4MTJ). By utilizing the differential MTJs with complementary states and positive feedback of cross-coupled inverters for sensing, the proposed 15T-4MTJ NV-TCAM cell can significantly improve the search reliability. Moreover, owing to that there is no static current during search operations, only dynamic charging and discharging current, it can achieve ultra-low power consumption. In addition, by using only one transistor as the critical path between the match-line and GND, its switch delay can be shortened, thereby realizing high-speed search operations. Hybrid CMOS/MTJ simulation results of the 144-bit word circuit show that the proposed 15T-4MTJ NV-TCAM cell can obtain a smaller search error rate of 2.7%, a higher search speed of 0.17 ns, and a lower search energy of 0.17 fJ/bit/search in comparison with other MTJ-based NV-TCAM cells. On the other hand, its write energy of 1.589 pJ/bit is about 3.64× smaller than that of the previously proposed 10T-4MTJ NV-TCAM cell.

Very large remanent polarization in ferroelectric Hf1-xZrxO2 grown on Ge substrates by plasma assisted atomic oxygen deposition

Plasma assisted atomic oxygen deposition was used to grow polycrystalline ferroelectric Hf1-xZrxO2 (x = 0.5–0.7) on technologically important (100) Germanium substrates showing sharp crystalline interfaces free of interfacial amorphous layers and strong evidence for the presence of a predominately orthorhombic phase. The electrical properties, evaluated using metal-ferroelectric-semiconductor (MFS) capacitors, show symmetric and robust ferroelectric hysteresis with weak or no wake-up effects. The MFS capacitors with x = 0.58 show very large remanent polarization up to 34.4 μC/cm2 or 30.6 μC/cm2 after correction for leakage and parasitics, combined with good endurance reaching 105 cycles at a cycling field of 2.3 MV/cm. The results show good prospects for the fabrication of Ge ferroelectric field effect transistors (FeFETs) for use in 1 T FeFET embedded nonvolatile memory cells with improved endurance.

Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits

Emerging non-volatile memories (NVMs) are known as promising alternatives to SRAMs in on-chip caches. However, their limited write endurance is a major challenge when NVMs are employed in these highly frequently written caches. Early wear-out of NVM cells makes the lifetime of the caches extremely insufficient for nowadays computational systems. Previous studies only addressed the lifetime of data part in the cache. This paper first demonstrates that the age bits field of the cache replacement algorithm is the most frequently written part of a cache block and its lifetime is shorter than that of data part by more than 27 $$\times$$ . Second, it investigates the effect of age bits wear-out on the cache operation and shows that the performance is severely degraded after even a small portion of age bits become non-operational. Third, a novel cache replacement algorithm, so-called Sleepy-LRU, is proposed to reduce the write activity of the age bits with negligible overheads. The evaluations show that Sleepy-LRU extends the lifetime of instruction and data caches to 3.63 $$\times$$ and 3.00 $$\times$$ , respectively, with an average of 0.06% performance overhead. In addition, Sleepy-LRU imposes no area and power consumption overhead.

Nonvolatile Memories Based on Graphene and Related 2D Materials.

The pervasiveness of information technologies is generating an impressive amount of data, which need to be accessed very quickly. Nonvolatile memories (NVMs) are making inroads into high-capacity storage to replace hard disk drives, fuelling the expansion of the global storage memory market. As silicon-based flash memories are approaching their fundamental limit, vertical stacking of multiple memory cell layers, innovative device concepts, and novel materials are being investigated. In this context, emerging 2D materials, such as graphene, transition metal dichalcogenides, and black phosphorous, offer a host of physical and chemical properties, which could both improve existing memory technologies and enable the next generation of low-cost, flexible, and wearable storage devices. Herein, an overview of graphene and related 2D materials (GRMs) in different types of NVM cells is provided, including resistive random-access, flash, magnetic and phase-change memories. The physical and chemical mechanisms underlying the switching of GRM-based memory devices studied in the last decade are discussed. Although at this stage most of the proof-of-concept devices investigated do not compete with state-of-the-art devices, a number of promising technological advancements have emerged. Here, the most relevant material properties and device structures are analyzed, emphasizing opportunities and challenges toward the realization of practical NVM devices.