Nonvolatile Memory Architecture Research Articles

A Reconfigurable Nonvolatile Memory Architecture for Prolonged Wearable Health Monitoring Devices

A Reconfigurable Nonvolatile Memory Architecture for Prolonged Wearable Health Monitoring Devices

Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures.

Non-volatile memory technology is now available in commodity hardware. This technology can be used as a backup memory for an external dram cache memory without needing to modify the software. However, the higher read and write latencies of non-volatile memory may exacerbate the memory wall problem. In this work we present a novel off-chip prefetch technique based on a Hidden Markov Model that specifically deals with the latency problem caused by complexity of off-chip memory access patterns. Firstly, we present a thorough analysis of off-chip memory access patterns to identify its complexity in multicore processors. Based on this study, we propose a prefetching module located in the llc which uses two small tables, and where the computational complexity of which is linear with the number of computing threads. Our Markov-based technique is able to keep track and make clustering of several simultaneous groups of memory accesses coming from multiple simultaneous threads in a multicore processor. It can quickly identify complex address groups and trigger prefetch with very high accuracy. Our simulations show an improvement of up to 76% in the hit ratio of an off-chip dram cache for multicore architecture over the conventional prefetch technique (g/dc). Also, the overhead of prefetch requests (failed prefetches) is reduced by 48% in single core simulations and by 83% in multicore simulations.

Memristive devices based on mass printed organic resistive switching layers

Resistive random-access memory is a candidate for next-generation non-volatile memory architectures. In this study, we use flexographic roll-to-roll printing technology for deposition of the resistive layer, a printing method that allows fast and cost-effective fabrication to create non-volatile resistive memory devices. Metal-free organic polymers blends composed of poly(methyl methacrylate) (PMMA) and a surplus of poly(vinyl alcohol) (PVA) serve as the active layer. Microscopic studies of the roll-to-roll printed layers show circular domains of PMMA embedded in PVA. The influence of the PMMA content in the polymer blend is investigated with respect to the performance and reliability of the resistive memory cells. Electrical characterization reveals a retention time of at least eleven days, a Roff/Ron ratio of approx. two orders and write/erase voltages of + 1/−2 V.

Orthogonal persistence in nonvolatile memory architectures: A persistent heap design and its implementation for a Java Virtual Machine

SummaryCurrent computer systems separate main memory from storage, and programming languages typically reflect this distinction using different representations for data in memory and storage. However, moving data back and forth between these different layers and representations compromise both programming and execution efficiency. To remedy this, the concept of orthogonal persistence (OP) was proposed in the early 1980s advocating that, from a programmer's standpoint, there should be no differences in the way that short‐term and long‐term data are manipulated. However, at that time, the underlying implementations still had to cope with the complexity of moving data across memory and storage. Today, recent nonvolatile memory (NVM) technologies, such as resistive RAM and phase‐change memory, allow main memory and storage to be collapsed into a single layer of persistent memory, opening the way for more efficient programming abstractions for handling persistence. In this work, we revisit OP concepts in the context of NVM architectures and propose a persistent heap design for languages with automatic memory management. We demonstrate how it can significantly increase programmer and execution efficiency, removing the impedance mismatch of crossing semantic boundaries. To validate and demonstrate the presented concepts, we present JaphaVM, an implementation of the proposed design based on JamVM, an open‐source Java Virtual Machine. Our results show that JaphaVM, in most cases, executes the same operations between one and two orders of magnitude faster than regular database‐based and file‐based implementations, while requiring significantly less lines of code.

Vehicle data management with specific wear-levelling and fault tolerance for hybrid DRAM-NVM memory

Abstract The emerging Non-Volatile Memory (NVM) attracts attentions in recent years because of its fast reading/writing speed, high density, low idle power and persistence. With such characteristics, NVM can be applied to application-specific embedded systems to improve performance such as automotive systems. However, NVM has limitation on writing operations and is consequently not suitable to be applied in writing sensitive systems. In this paper, we propose a Vehicle Data Management (VDM) approach based on a hybrid DRAM and NVM architecture for automotive systems. VDM approach includes automotive dynamic data management, vehicle-specific wear-levelling and vehicle fault tolerance. Automotive dynamic data management can distinguish the hot or cold data from vehicle Electronic Control Units (ECUs) and sensors, and then manage the data to reduce the writing operations on NVM for the hybrid main memory. Vehicle-specific wear-levelling can balance the wear to prolong the lifetime of NVM. A fault tolerance mechanism is also provided for NVM to recover the fault blocks. The experimental results show that both automotive dynamic data management and vehicle-specific wear-levelling can effectively reduce the writing operations compared with other approaches. Vehicle fault tolerance can achieve a high recovery rate and a low time overhead when error rate is not very high.

RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses

Although emerging non-volatile memories (NVMs) have been comprehensively studied to design next-generation memory systems, the symmetry of the crossbar structure adopted by most NVMs has not been addressed. In this work, we argue that crossbar-based NVMs can enable dual-addressing memory architecture, i.e., RC-NVM, to support both row- and column-oriented memory accesses for workloads with different access patterns. Through circuit-level analysis, we first prove that such a dual-addressing architecture is only practical with crossbar-based NVMs rather than DRAM. Then, we introduce the RC-NVM architecture from bank, chip and module levels, and propose RC-NVM aware memory controller. We also address the challenges to implement the end-to-end RC-NVM system. Especially, we design a novel protocol to solve the cache synonym problem with very little overhead. Finally, we introduce the deployment of RC-NVM for in-memory databases (IMDBs) and evaluate its performance with IMDBs and well-optimized general matrix multiply (GEMM) workloads. Experimental results show that with only 10 percent area overhead 1) the memory access performance of IMDBs can be improved up to 14.5X, and 2) for GEMM, RC-NVM naturally supports SIMD operations and outperforms the best tiled layout by 19 percent.

Exploring the Dynamics of Real-World Memristors on the Basis of Circuit Theoretic Model Predictions

The memristor represents the key circuit element for the development of the constitutive blocks of future non-volatile memory architectures and neuromorphic systems. However, resistance switching memories offer a plethora of further opportunities for the electronics of the future. By virtue of the compatibility between the well-established CMOS technology and the fabrication process of most memristors, the exploitation of the peculiar dynamic behaviour of resistance switching memories, which, in general, differ depending upon their material composition, may allow the development of new circuits, which, processing information in unconventional forms, may extend and/or complement the functionalities of state-of-the-art electronic systems. Further, the attractive capability of real-world non-volatile memristors to store and process information in the same physical nanoscale location open the fascinating opportunity to improve the low throughput of Von Neumann computing machines, due to the limited bandwidth of the bus transferring data between the memory and the central processing unit. Finally, the extreme sensitivity of their electrical behaviour to small changes in their initial condition/input and the intrinsic stochastic variability in their switching dynamics may be harnessed to develop innovative bio-signal sensors as well as new cryptographic circuits and systems. The derivation of accurate mathematical models for the electrical behaviour of real-world memristor nano-devices, and their later circuit- and system-theoretic investigation aimed at drawing a comprehensive picture of their peculiar nonlinear dynamic behaviour under the set of inputs and initial conditions expected of the application of interest are fundamental steps towards their conscious future use in integrated circuit design. With this in mind, the present paper adopts a powerful theoretic tool known as Dynamic Route Map to analyse some of the most reliable physics-based models of real-world resistance switching memories to reveal how a particular dynamic phenomenon, known as fading memory, and recently discovered in a tantalum oxide non-volatile memristor device fabricated at Hewlett Packard Labs, is ubiquitous at nanoscale. The physical mechanisms behind the emergence of history-erase effects in non-volatile memristor nano-devices is explained thoroughly for both the DC and the AC periodic excitation scenarios.

Experimental dynamic trapping of electrostatically actuated bistable micro-beams.

We demonstrate dynamic snap-through from a primary to a secondary statically inaccessible stable configuration in single crystal silicon, curved, doubly clamped micromechanical beam structures. Nanoscale motion of the fabricated bistable micromechanical devices was transduced using a high speed camera. Our experimental and theoretical results collectively show, that the transition between the two stable states was solely achieved by a tailored time dependent electrostatic actuation. Fast imaging of micromechanical motion allowed for direct visualization of dynamic trapping at the statically inaccessible state. These results further suggest that our direct dynamic actuation transcends prevalent limitations in controlling geometrically non-linear microstructures, and may have applications extending to multi-stable, topologically optimized micromechanical logic and non-volatile memory architectures.

Novel device structure for phase change memory toward low-current operation

We present a novel device architecture for low set and reset currents in phase change random access memory (PCRAM). In this structure, the sidewall of phase-change film is contacted with the vertical heating layer. In particular, to realize a small contact area of under 50 nm2 for low reset current, this structure includes stacked layers consisting of extremely thin phase change material (PCM) and conduction films, the fabrication method of which is proposed. We estimated set and reset currents for the proposed structure by the device simulation method. Here, we confirmed that a contact area of 30 nm2 in this structure, where Ge2Sb2Te5 is used as PCM, provides a reset current of 13.5 µA and a set current of 4 µA, which are promising for the scaling down of PCM. Furthermore, it is confirmed that the thinner PCM in this structure provides less thermal disturbance to the neighboring cell. From the results, we expect this structure to be a promising candidate for a high-density nonvolatile memory architecture with PCM.

Cache Optimization Approaches of Emerging Non-Volatile Memory Architecture:A Survey

Cache Optimization Approaches of Emerging Non-Volatile Memory Architecture:A Survey

Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage

For highly scalable NAND flash memory applications, a compact (4F2/cell) nonvolatile memory architecture is proposed and investigated via threedimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories

In this paper we present a 3D simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories. First, the simulation methodology is introduced and validated against experimental data. Then, physical effects that significantly impact the coupling calculation are pointed out. Finally, the method is applied to a sensitivity study of both gate coupling and gate cross-interference in different non-volatile memory architectures showing the increasing importance of this kind of analysis in designing more advanced technologies.

A spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) with a ferromagnetic semiconductor for the channel

We propose and theoretically analyze a metal-oxide-semiconductor field-effect-transistor type of spin transistor (spin MOSFET) employing a ferromagnetic semiconductor (FS) for the channel. A ferromagnetic Schottky junction between the FS channel and a ferromagnetic metal (FM) is used for the source and drain. The output characteristics of the spin MOSFET depend on the relative magnetization configuration of the FS channel and FM source/drain. A large magnetocurrent ratio can be obtained and it is insensitive to the drain-source bias conditions, owing to the spin-filter effect of the FS/FM Schottky junction. Furthermore, excellent transistor performance, such as high transconductance and small subthreshold swing, is predicted. A new nonvolatile memory architecture using a single spin MOSFET cell is also presented, in which the programming current can be drastically reduced using the electrical manipulation of magnetization reversal of the FS channel.

Low temperature processing of Nb-doped Pb(Zr,Ti)O3 capacitors with La0.5Sr0.5CoO3 electrodes

The effect of crystallization temperature on the electrical properties of sol-gel derived Pb(Zr,Ti,Nb)O3 or PNZT capacitors with La0.5Sr0.5CoO3 (LSCO) electrodes has been investigated. It is demonstrated that LSCO//PNZT(4/30/70)//LSCO capacitors can be fabricated at temperatures as low as 550 °C without significant degradation in their ferroelectric and dielectric properties. Lowering the process temperature to 500 °C resulted in substantial degradation in capacitor properties. Nonetheless, all capacitors processed in the 500 °C to 675 °C range exhibited essentially no fatigue up to 5×109 switching cycles. The low temperature processing is significant as it indicates that this ferroelectric capacitor technology is compatible with high density nonvolatile memory architectures. In other words, these process temperatures are low enough to maintain plug integrity and to prevent degradation of the underlying CMOS circuitry in a high density ferroelectric memory.