Non-ideal Analysis Research Articles

Design of novel oscillator circuit using grounded capacitors and two current mode building blocks

ABSTRACT This paper introduces a new scheme of oscillator realisation and its implementation in the form of a novel circuit, which requires two current mode building blocks and two grounded capacitors, besides two resistors. The proposed circuit generates two sinusoidal voltage outputs and operates on ±2.5 V supply voltage. The parasitic and non-ideal analysis of the proposed circuit is given. PSPICE simulation results are included in support of the proposed theory. The new proposed circuit is compatible to CMOS technology. Several possible applications are suggested as conclusive discussion to justify the new advance.

Adaptive Antenna Array Based Non-Cooperative Co-Channel Interference Cancellation System for Ultrashort Wave Radios and Non-Ideality Analysis

Adaptive Antenna Array Based Non-Cooperative Co-Channel Interference Cancellation System for Ultrashort Wave Radios and Non-Ideality Analysis

Deviation Analysis of Multiport VNA Hardware Specification-related Nonideality

Deviation Analysis of Multiport VNA Hardware Specification-related Nonideality

First-Order Universal Active Filter Configuration Using Single VCII+

A new universal active filter configuration is presented in this paper which is capable of realizing all three first-order filter responses namely all pass (AP), low pass (LP) and high pass (HP) using a single second generation voltage conveyor (VCII+), a virtually grounded capacitor and two resistors. The proposed circuit offers tunability of the cut-off frequency, gain (for HP filter) and simultaneous availability of two filter outputs, one at a low impedance node (HP/AP), the other output, namely the LPF will require a voltage buffer to avoid loading. The nonideal analysis of filter responses based on the nonideal model of VCII+ is carried out by considering all the parasitic immittances and nonideal gains and found that they have no significant effect on the performance of the proposed filter structure. Sensitivity analysis with respect to active and passive components has also been carried out. The functionality of the presented circuit has been validated through simulations and experimental results, where the VCII+ was implemented using the macro model of the commercially available CFOA IC AD844. Additionally, the proposed circuit has been tested using a CMOS VCII+ implemented with 0.18[Formula: see text][Formula: see text]m TSMC technology parameters. The tests include advanced evaluations based on Monte Carlo simulations.

Single CDBA-based grounded parallel lossy inductor simulator circuits

Two new configurations for the realization of lossy grounded inductor each employing one current differencing buffered amplifier (CDBA), three resistors, a voltage follower and one grounded capacitor are presented. The realized inductances from the proposed configurations have independent tunability through a single resistor. The proposed circuits make use of the intrinsic current differencing property of CDBAs by not leaving any of its input terminals open or connected to ground. Both the presented circuits use grounded capacitor (which is particularly attractive for integrated circuit implementation) connected at the Z-terminal of CDBA which may also absorb the parasitic capacitance. The proposed lossy inductors can be used in applications such as low frequency sinusoidal oscillator, low pass filter (LPF) and band pass filter (BPF). Such examples may be suitable from the viewpoint of biomedical instrumentation and geo-physical applications. Non-ideal analysis has been carried out to support the theoretical propositions for both the proposed circuits. PSPICE simulation results with CMOS CDBA have been presented to establish the workability of the proposed lossy inductor structures. Experimental results using commercially available AD844 ICs have also been included to demonstrate the viability of the proposed lossy inductors based on CDBAs.

Macro Model for Discrete-Time Sigma‒Delta Modulators

This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

Resistor-Less Capacitor-Controlled Single VDIBA-Based Third-Order Quadrature Sinusoidal Oscillator

This paper presents a new voltage-mode (VM) third-order quadrature sinusoidal oscillator (TOQSO) employing a single voltage differencing inverting buffered amplifier (VDIBA) along with three grounded capacitors (GCs) (suitable for IC implementation and also for parasitic absorption) and two NMOS transistors (operated in triode region). The condition of oscillation (CO) and frequency of oscillation (FO) of the presented circuit are self-regulating, i.e. CO can be regulated electronically by transconductance and by varying capacitors, and the FO can be tuned. Non-ideal analysis of the presented TOQSO circuit has been carried out and the results have been compared with ideal ones. Sensitivities of FO with respect to active and passive components have been evaluated and found to be less and also the presented oscillator configuration has low power dissipation and low total harmonic distortions (THD). The feasibility of the presented circuit has been validated using high-performance tunable CMOS VDIBA with a low supply voltage ±0.6 V. Experimental results have also been corroborated using VDIBA, implemented with commercially available ICs MAX435 and AD830.

Fully Differential Current-Mode Configuration for the Realization of First-Order Filters with Ease of Cascadability

It is well known that fully differential signal processing is more advantageous than single-ended signal processing in a noisy environment, and is widely used in audio, video and other signal processing applications. This paper introduces a new fully differential configuration that contains a first-order low-pass (LP) filter, high-pass (HP) filter, and all-pass (AP) filter, all present within the same circuit design. The proposed fully differential configuration is simple and employs only one multiple-output current differencing transconductance amplifier and one grounded capacitor. The circuit has a wide operating frequency range (up to 73 MHz). The additional features offered by the proposed circuit include use of the lowest number of active and passive components, suitability of the integrated circuit chip, support of cascadability, electronic tunability, no passive component-matching restrictions, availability of all first-order responses, i.e., LP, HP, and AP, and low-level operating supply voltages. Non-ideal and parasitic analyses are investigated for the proposed circuit, and PSPICE simulation results are presented to verify the proposed theory. Additionally, the proposed fully differential LP filter circuit is experimentally verified using off-the-shelf ICs. Moreover, the cascading feasibility is demonstrated by realizing a fully differential nth-order LP filter.

A Nonisolated Transformerless High-Gain DC–DC Converter for Renewable Energy Applications

Dc–dc converters with a high gain, continuous input current, and common ground are usually employed in renewable energy applications to boost the generated output voltage of renewable energy sources. In this paper, a high-gain dc–dc converter comprising a voltage multiplier cell (VMC) and a common ground with continuous input current and low-voltage stress across semiconductor devices is proposed. The converter produces a voltage gain of about ten times compared to the conventional boost converter at a duty ratio of 50% by utilizing switched capacitors and switched inductors. The simultaneous operation of both the switches with the same gate pulse offers easy and simple control of the proposed converter with a wide range of operations. The boundary operation of the converter is analyzed and presented in both modes, i.e., continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Ideal and nonideal analysis of the converter is carried out by integrating real models of passive elements and semiconductor devices by using PLECS software. The simulation is also used to calculate the losses and hence the working efficiency of the converter. The performance of the converter analyzed in the steady state is compared with various similar converters based on the voltage boosting capability and switching stresses. A hardware prototype is also developed to confirm and validate the theoretical analysis and simulation of the proposed converter.

Mixed-Mode Electronically-Tunable First-Order Universal Filter Structure Employing Operational Transconductance Amplifiers

In this paper, a new mixed-mode first-order universal filter configuration is presented that employs three operational transconductance amplifiers (OTAs) and one grounded capacitor (eminently suitable for IC chip fabrication). All three first-order generic filter functions, namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) in all the four possible modes, namely voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) can be realized. The proposed configuration offers high input impedance and high output impedance. The pole frequency of the filter can be controlled electronically by varying a single transconductance. Nonideal analysis of the proposed filter structure has also been carried out and the results have been compared with those obtained from ideal analysis. The performance of the presented filter configuration has been corroborated through PSPICE simulations as well as experimental results. The various simulation and experimental results validate the practical viability of the proposed configurations.

New Resistor-Less Electronically Controllable ±C Simulator Employing VCII, DVCC, and a Grounded Capacitor

In this paper, a new realization of electronically controllable positive and negative floating capacitor multiplier (±C) is presented. The peculiarity of the presented topology is that, for the first time, it implements a floating equivalent capacitor between its two input terminals, rather than a grounded one. To achieve the best performance, we simultaneously use the advantages provided by the current conveyor and its dual circuit, the voltage conveyor. The proposed topology is resistor free and employs one dual-output second-generation voltage conveyor (VCII±) and one electronically tunable differential voltage current conveyor (E-DVCC) as active building blocks (ABBs) and a single grounded capacitor. The value of the simulated capacitor is controlled by means of a control voltage VC which is used to control the current gain between X and Z terminals of E-DVCC. The circuit is free from any matching condition. A complete non-ideal analysis by considering parasitic impedances as well as non-ideal current and voltage gains of the used ABBs is presented. The proposed circuit is designed at the transistor level in 0.18 µm and ±0.9 V supply voltage. Simulation results using the SPICE program show a multiplication factor ranging from ±10 to ±25.4 with a maximum error of 0.56%. As an example, the application of the achieved floating capacitor as a standard high pass filter is also included.

Contribution from non-ideality and preferential solvation to non-linear solvatochromism in binary mixtures

The knowledge of preferential solvation is of critical importance in description of the solute behavior in mixed solvents. The analysis of solvatochromic shifts as a function of solvent composition is popular in this regard, since it gives molecular information on solute-solvent interactions. However, due to the complexity of the interactions and possible non-ideality of mixed solvents, implementing an efficient approach for interpretation of solvent-solvent interactions is an opening major challenge in modeling solvatochromism to get reliable results on preferential solvation. Here, we proposed a new methodology to treat solvatochromism in solvent mixtures in order to reach a more reliable picture of the local composition around the solute. As the main idea, the effect of solvent-solvent interactions on spectral shift was considered by formulating the non-ideality of solvent in solvation shell of the solute as a function of the local composition by exploiting the results obtained from the analysis of the bulk mixture non-ideality. From that, the non-linear variation in spectral shift can be well separated into contributions from preferential solvation and the local non-ideality. To test this approach, solvatochroimsm of 2-methyl-4-nitroaniline was studied in some mono-solvents and binary mixtures. The spectral properties of 2-methyl-4-nitroaniline and its response to solvent were rationalized by quantum chemical calculation and linear solvation energy relationships analysis in mono-solvents. Then, the observed strong non-linear solvatochromism of 2-methyl-4-nitroaniline in aqueous mixtures of ethanol, DMF and DMSO was treated by the proposed model that provided both physically and statistically more reliable results on preferential solvation and molecular interactions, with respect to the other widely-used solvent exchange models. As an interesting and important result, non-ideality, but not preferential solvation, was responsible for non-linear solvatochromism in aqueous solutions of ethanol and DMF.

A new high frequency MOS-C TOETQO employing DXCCTA

ABSTRACT This research paper reports a high frequency Third Order Electronically Tunable Quadrature Oscillator (TOETQO) using an active element termed as Dual-X Current Conveyor Transconductor Amplifier (DXCCTA) in which active element MOS and passive Capacitor (C) contribute the implementation performance of the proposed design as MOS-C TOETQO. Due to the presence of DXCCTA with active grounded capacitor and MOS-based resistor, the proposed quadrature oscillator facilitates a suitable design for integrated circuits (ICs). The proposed TOETQO circuit produces current as well as voltage outputs simultaneously. Moreover, the non-ideal analysis of the proposed oscillator circuit is also included. The proposed design shows a good agreement for the oscillation criteria due to the acceptable limit of %THD and gives the variation in frequency of oscillation (up to MHz) values with respect to bias current. Moreover, by keeping the bias current constant, frequency of oscillation can also be electronically tuned independently by varying the values of resistor. Finally, Cadence simulation results are depicted to verify the theoretical analyses and practical feasibility of proposed TOETQO design is also well verified with experimental set up by using IC AD844 and CA3080. A fair comparison of the proposed quadrature oscillator with existing literatures is also tabulated.

High Efficiency and Voltage Conversion Ratio Bidirectional Isolated DC-DC Converter for Energy Storage System

This paper proposes a high efficiency and conversion ratio bidirectional isolated DC-DC converter with three-winding coupled inductor, which can fulfil storage system charging and discharging. The proposed topology is improved from traditional Buck-Boost converter. By integrating coupled inductor and switched-capacitor into power stage, the proposed converter can achieve the merits of isolation and bidirectional power flow. The proposed topology has only four switches and a common core coupled inductor, which greatly reduces design costs and achieves high step-up/step-down voltage gain without excessive duty cycles or high turns ratios. In addition, the proposed also has the function of leakage inductance energy recovery, which can recover all the energy stored in the leakage inductance to improve efficiency, and the main switches has a zero voltage switching (ZVS) feature. This paper implements a 500 W converter to verify the feasibility of the proposed topology through software simulation and experiment results, and conducts theoretical analysis, formula derivation, operation principle analysis, and non-ideal analysis. Finally, the experimental results show that the highest efficiency of the step-up and step-down modes are 96.8% and 96.4%, respectively.

Novel Fractional-Order Current-Mode VCOs/SRCOs with All-Grounded-Passive-Elements

Five new structures of linear fractional-order voltage-controlled oscillators (FO-VCOs) utilizing only Multiplication-Mode Current Conveyors (MMCCs) and canonic numbers of all grounded passive elements (AGPEs) are presented in this paper. The derivation procedure has been detailed along with the relevant nonideal analysis. The work also presents three fractional-order cases of the oscillators and brings out the effects of port nonidealities and port parasitics on the performance of presented FO-VCOs. The workability of all the five new FO-VCOs has been validated on PSPICE utilizing library files of AD844 and AD835 for realizing MMCC employed in the FO-VCOs. For all the three special fractional-order cases, the simulation results have been tabulated along with relevant MATLAB plots that facilitate comparison among oscillation parameters and the fractional order. The harmonic distortion figures have been found out by Fourier analysis. Experimental workability of a VCO, employing MMCC realized with AD835 and AD844 of our investigation is included to support hardware functionality.

Analysis of non-idealities in rhomb compensators.

In-line rotatable rhombs that are only weakly chromatic are desired as compensators for a wide variety of applications in spectroscopic polarimetry and Mueller matrix spectroscopic ellipsometry. These devices employ multiple total internal reflections to generate differences in the phase shifts upon reflection for orthogonal fast and slow axis optical electric field components. A framework has been developed for characterization of non-idealities in the performance of rhombs due to dissipation and associated dichroism upon each reflection as well as stress-induced birefringence along each beam path. External oblique reflection measurements by spectroscopic ellipsometry for the internally reflecting interface structures has enabled characterization of the dichroic effects and retardance generated by the reflections. The framework for analysis of the effects of stress relies on simulations demonstrating that the contributions to polarization modification from each beam path depend only on the accumulated stress-induced retardance and average azimuthal angle of the fast principal stress axis along the given path. The overall approach has been applied to straight-through Mueller matrix measurements of a three-reflection rhomb in its operational configuration to establish the set of stress parameters for each of the four beam paths needed to fit the measurements. Thus, device geometry and optical structure, including layer thicknesses and component media optical properties, as well as stress-induced retardances and average stress azimuthal angles, which are all deduced in the analysis, enable a complete description of the polarization modifying properties of the rhomb when serving as a compensator.

Analysis of Non-Idealities on CMOS Passive Mixers

In the current state of the art, WiFi-alike standards require achieving a high Image Rejection Ratio (IRR) while having low power consumption. Thus, quadrature structures based on passive ring mixers offer an attractive and widely used solution, as they can achieve a high IRR while being a passive block. However, it is not easy for the designer to know when a simple quadrature scheme is enough and when they should aim for a double quadrature structure approach, as the latter can improve the performance at the cost of requiring more area and complexity. This study focuses on the IRR, which crucially depends on the symmetry between the I and Q branches. Non-idealities (component mismatches, parasitics, etc.) will degrade the ideal balance by affecting the mixer and/or following/previous stages. This paper analyses the effect of imbalances, providing the constraints for obtaining a 40 dB IRR in the case of a conversion from a one-hundred-megahertz signal to the five-gigahertz range (upconversion) and vice versa (downconversion) for simple and double quadrature schemes. All simulations were carried out with complete device models from 65 nm standard CMOS technology and also a post-layout Monte Carlo analysis was included for mismatch analysis. The final section includes guidelines to help designers choose the most adequate scheme for each case.

Realization of Generalized Current-Mode Multifunction Filter

In this work, a three-input single-output structure of current-mode second-order multifunction filter is presented. Two multiple-output second-generation current conveyors serve as the active building blocks. Additionally, two grounded resistors and two grounded capacitors are employed as passive components. On appropriate selection of the input values, all second-order filter functionalities, namely, low-pass, high-pass, all-pass, band-pass and band-reject, can be availed. Proposed filter shows good sensitivity performance and supports high frequency operation. Non-ideal analysis is presented to show the intactness of filter characteristics under runtime conditions. Simulation results show good correlation with the theoretical performance of the proposed filter.

Two-CFOA-grounded-capacitor first-order all-pass filter configurations with ideally infinite input impedance

Recently, Yuce, Verma, Pandey and Minaei presented two interesting current feedback operational amplifier (CFOA)-based first-order all pass filter (APF) configurations employing a single grounded capacitor (GC). Their first circuit employs only two CFOAs (along with five resistors) but does not have ideally infinite input impedance; the second circuit although does possess ideally infinite input impedance but requires three CFOAs (along with five resistors). In this paper, we present six new GC-APFs which employ only two CFOAs and yet provide infinite input impedance with a reduced number of only three/four resistors than the quoted earlier circuits. A non-ideal analysis of all the proposed circuits has been carried out and the workability and utility of the proposed circuits has been corroborated by the SPICE simulation and hardware implementation results using AD844-type IC CFOAs. This paper, thus, adds a number of interesting alternatives to the CFOA-based first-order APFs presented in the mentioned earlier work.

New floating/grounded FDNC and non-ideal grounded FDNR simulators based on VDTA

The paper proposes a new grounded/floating frequency dependent negative conductance (FDNC) simulator, and a non-ideal frequency dependent negative resistance (FDNR) simulator, based on deployment of voltage differencing transconductance amplifiers (VDTA), along with two grounded capacitances. The presented simulators feature electronic controllability of realized negative conductance/resistance via DC bias current of VDTA, with no component matching constraints. The non-ideality analysis of the circuits is also presented. The proposed solutions exhibit an excellent behaviour under non-ideal conditions with low active/passive sensitivity. The working of the presented simulators has been verified by corresponding voltage mode filter design examples, and has been verified by HSPICE simulations which were carried out on the basis of 0.18 μm CMOS technology.