Non-dominant Pole Research Articles

A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage

A novel non-inverting pull–push gain stage output-capacitorless low-dropout regulator (OCL-LDO) is introduced, designed specifically for power management of system-on-chip (SoC). The incorporation of an innovative non-inverting gain stage (NIGS) serves to shift the non-dominant parasitic poles to higher frequencies, thereby enhancing the overall stability of the system. The proposed pull-push configuration markedly improves the slew rate limitation at the gate of the power transistor. Post-layout simulation outcomes, corroborated through a 180-nm CMOS fabrication process, indicate that the proposed LDO regulator maintains stability across a wide range of loading currents, from 0 mA to 100 mA, with a Miller compensation capacitance of only 3.5 pF. The circuit operates with a quiescent current of 143 μA when powered by a 1.5 V single supply. The LDO regulator boasts a dropout voltage of 300 mV, enabling it to deliver up to 100 mA of load current. Simulation results show that the undershoot voltage is only 63.7 mV when the load current jumps from 0 to 100 mA with edge of 100 ns, while employing a 100 pF capacitance load. The recovery time to return to equilibrium post this abrupt change is approximately 0.15 μs. The proposed OCL-LDO regulator exhibits a substantial enhancement in transient response compared to its predecessors, alongside a harmonized balance between line regulation and load regulation performance parameters.

Stabilizing regions of dominant pole placement for second order lead processes with time delay using filtered PID controllers.

In order to handle second order lead processes with time delay, this paper provides a unique dominant pole placement based filtered PID controller design approach. This method does not require any finite term approximation like Pade to obtain the quasi-polynomial characteristic polynomial, arising due to the presence of the time delay term. The continuous time second order plus time delay systems with zero (SOPTDZ) are discretized using a pole-zero matching method with specified sampling time, where the transcendental exponential delay terms are converted into a finite number of poles. The pole-zero matching discretization approach with a predetermined sampling period is also used to discretize the continuous time filtered PID controller. As a result, it is not necessary to use any approximate discretization technique, such as Euler or Tustin, to derive the corresponding discrete time PID controller from its continuous time counterpart. The analytical expressions for discrete time dominant pole placement based filtered PID controllers are obtained using the coefficient matching approach, while two distinct kinds of non-dominant poles, namely all real and all complex conjugate, have been taken into consideration. The stabilizable region in the controller and design parameter space for the chosen class of linear second order time delay systems with lead is numerically approximated using the particle swarm optimization (PSO) based random search technique. The efficacy of the proposed method has been validated on a class of SOPTDZ systems including stable, integrating, unstable processes with minimum as well as non-minimum phase zeros.

Design of simple nonovershooting controllers for linear high order systems with or without time delay

In this paper, we mainly considered the problem of nonovershooting control of high order systems with or without time delay by simple controllers. As basic principles for nonovershooting control systems, three propositions are offered and proved. Under direction of these principles, a nonovershooting dominant pole control structure having three dominant poles, i.e., one real pole and a pair of complex conjugate poles on its left, is proposed. While its zeroes and nondominant poles are on the left side of these three dominant poles with sufficient distance. The controllers adopted are composed by first order filter and PD-PID controller. Dominance of the three dominant poles can be checked and ensured through the computational method we offered. Two illustrating examples are given to show the effectiveness of our method.

An Improved Circuit of Super Source Follower Based on gm-boosting Technology

An improved circuit of super source follower (SSF) based on gm-boosting technology is proposed in this paper. The traditional SSF circuit is used to reduce the output impedance of the source follower, to provide stronger load capacity as the output stage of the whole circuit, or to push the non-dominant poles in the multi-stage amplifier circuit to a higher frequency position. In the paper, based on the above SSF circuit, an operational amplifier is connected in parallel between the gate and drain of the Nmos as the feedback loop, which takes the drain as the positive input and the gate as the output to form the gm-boosting structure. The advantage of this structure is to further reduce the output resistance through the voltage-voltage feedback characteristics of the gm-boosting structure. Because two loops are formed after adding the structure, as long as the open-loop gain of the operational amplifier is high enough, the loop formed by the operational amplifier will occupy a dominant position, thus shielding the influence of the source follower on the overall output resistance. The output resistance can change with the operational amplifier gain. The simulation results show that the output impedance of the circuit is only about 92 Ω, which is much lower than 1 kΩ of SSF structure.

A high current efficiency multipath nested feedforward compensation technique for two-stage amplifier

In this paper, a high current efficiency two-stage amplifier using multipath nested feedforward compensation (MNFC) method is proposed. For the purpose of achieving the high current efficiency, the first stage of the amplifier uses a recycling folded cascode amplifier (RFC) and a nested small-gain stage is added between the two stages of the amplifier so that there are two paths in the feedforward path. This two-stage amplifier improves the phase margin (PM) and extends the gain bandwidth (GBW) by using the MNFC technique which can eliminate the non-dominant pole. The chip area of this two-stage MNFC amplifier which using 0.18μm CMOS process is 0.01272 mm2. The simulated and measured results shows that the phase margin(PM), DC gain, gain-bandwidth(GBW), average 1% settling time, slew rate- (SR-) and slew rate+ (SR+) is 72.7°, 104.4 dB, 4.29 MHz, 246.2 ns, 16 V/μs, and 6.15 V/μs, respectively, when the load capacitance is 120 pF. The supply voltage of this circuit is 1.8 V and the power consumption is 0.13 mW.

Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings

This article presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry island and monotonic current flow while minimizing wire crossings. The nodes along the signal paths in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placement methods introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially the dominant and the first non-dominant poles and wire crossings among critical nets, may increase wire load and performance degradation. This article proposes a pole-aware analog layout synthesis methodology to minimize the total wire load and wire crossings while satisfying different symmetry and topological routing constraints. Using a strong-connectivity approach to the group Steiner problem, the presented method for automatic selection of port locations can help reduce total wirelength, increase routing flexibility, and minimize total wire crossings. Experimental results show that the proposed approach results in better solution quality in circuit performance compared with other recent works.

A Nested Miller Compensation with a large feed-forward transconductor for capacitor-less flipped voltage follower low dropout regulator

In this paper, a capacitor-less flipped voltage follower (FVF) low dropout (LDO) regulator using nested miller compensation with a large feed-forward transconductor (NMCLFT) is presented. The LDO regulator is a dual-summing based three-stage high-gain structure and NMCLFT stabilizes the feedback loop for the load current ranges of 0 to 50 mA with load capacitances of 0 to 100 pF. This LDO regulator uses the multiple feed-forward paths which enhance the unity gain bandwidth (UGB) as well as the transient responses. The large feed-forward transconductor separates the non-dominant complex poles of nested miller compensation (NMC) into two simple poles and pushes one of the poles into high-frequency. It also provides a strong low-frequency left-half plane (LHP) zero and pushes right-half plane (RHP) zero of NMC into high-frequency and makes the multi-pole LDO regulator into a single-pole LDO for all the cases, from light load to heavy load with different load capacitor corners. The NMCLFT eliminates the minimum load current and minimum load capacitance constraints with improved transient response. The proposed LDO regulator achieves the settling time of 120 ns with the minimum edge time of 10 ns for the load current ranges of 0 to 50 mA and the load capacitance ranges of 0 to 100 pF. This LDO is implemented in 130 nm CMOS technology and it consumes a quiescent current of 63μA.

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution. High-speed feedback pathways relying on Miller capacitors and current buffers are implemented within the amplifier scheme to push the non-dominant poles to high frequencies for small to medium load capacitors. A small resistor is also shared between the two pathways to improve the stability regardless of the load capacitor. A serial <inline-formula> <tex-math notation="LaTeX">$R$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula> branch is then added to extend the lower limit of load drive capability to small load capacitors. Gain margin is, for the first time in literature, analytically evaluated and included in the design phase. A prototype of the proposed amplifier is fabricated in 65-nm CMOS process with active area of 0.0017 mm² and 1.15 pF total compensation capacitance. It can drive the load capacitor range from 200 pF to 100 nF, while drawing a quiescent current of <inline-formula> <tex-math notation="LaTeX">$7.4~ \mu \text{A}$ </tex-math></inline-formula> from a 1.2-V input voltage supply. A unity-gain frequency of 1.67 MHz was measured with an average slew-rate of 1.31 V/<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, when the proposed amplifier is wired in unity-gain configuration to drive a 500-pF load capacitor.

A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

In this paper, a simple while effective methodology to calculate the symbolic transfer function of a multistage amplifier with frequency compensation is proposed. Three general amplifier models are introduced and analyzed, which represent basic topologies found in the literature. For these amplifier models, the symbolic transfer function is derived and specific strategies for the zero and non-dominant pole expressions are presented. The methodology is suited for hand calculations and yields accurate results while offering more intuition into the operation of the widely adopted frequency compensation solutions discussed in the literature. The effectiveness of the proposed approach is validated through various typical cases of study.

A High Bandwidth-Power Efficiency, Low THD2,3 Driver Amplifier with Dual-Loop Active Frequency Compensation for High-Speed Applications

This paper presents a driver amplifier with high bandwidth-power efficiency, high capacitor-driving capacity, and low total harmonic distortion (THD). One complementary differential pair composed of self-cascode transistors is incorporated to obtain a full input voltage swing. Flipped voltage follower (FVF) buffers are applied as second stage to drive the last class-AB output stage. Moreover, a dual-loop active-feedback frequency compensation (DLAFC) is presented, which can stabilize the proposed multistage amplifier and keep the dominant pole on high frequency to obtain high-frequency total harmonic distortion (THD) suppression. To achieve a low-frequency phase margin protection (PMP), one left half-plane (LHP) zero is introduced to compensate for the nondominant pole caused by the load capacitor. Meanwhile, two high-frequency LHP zeros are injected to achieve high-frequency phase margin boosting (PMB) and reduce the amplifier’s settling time and integration area. This proposed amplifier is implemented in a standard DBH 0.18 μm 5 V CMOS process, and it achieves over 115-dB DC gain, 150–300 MHz GBW under 0–100 p load capacitors, ultra-high THD2,3 suppression ranges from 100 kHz to 10 MHz under 1–2 V output swing, and over 250 V/μs average slew rate, by only dissipating 12.5 mW at 5 V power supply.

High-Speed Low-Power Rail-to-Rail Buffer using Dynamic-Current Feedback for OLED Source Driver Applications

In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer’s first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm $$\times$$ 59 μm).

Probability distribution function of crossover frequency of operational amplifiers

For the first time the cumulative distribution function and histogram of the crossover frequency of a contemporary operational amplifier ADA4898-2 is experimentally studied. Using a USB lock–in amplifier, which allows automatic frequency sweep of the current response of a non-inverting amplifier with significant static amplification, we measure the crossover frequency of 200 samples of ADA4898-2 operational amplifiers. This new method gives a significant advantage in accuracy and speed of study of every operational amplifier. The theory we use is based on the universal relation between time dependent output and input voltages. This common relation for all operational amplifiers is applicable for frequencies much smaller than the crossover frequency and the frequencies of non-dominant poles. In other words, this approximation is adequate, when an operational amplifier is included in a circuit with significant amplification.

A Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator

A novel internal compensation technique named dual frequency compensation is proposed to improve the stability and the transient response of the on-chip output capacitor three stage low-drop-out linear voltage regulator (LDO). It exploits a combination of amplification and differentiation to sufficiently separate the dominant pole from the first non-dominant pole so that the latter is located after the unity gain frequency regardless of the load current value. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18 µm low voltage CMOS technology. The presented LDO regulator delivers a stable voltage of 1.2 V for an input supply voltage range of 1.35-1.85 V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is 54.5 mV when the load current pulses from 150mA to 0mA during a fall time of 1µs. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.

Ultra-Wide Bandwidth Fully Differential CMOS Opamp with a Novel Bandwidth Extension Technique for SoC Active Filter Applications

An ultra-wide bandwidth fully differential two-stage 65[Formula: see text]nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called “pole duplication”. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103[Formula: see text]MHz 3-dB bandwidth with a 2[Formula: see text]pF load capacitor. It consumes 9[Formula: see text]mA current from 1.2-V supply. Transition frequency of 2.4[Formula: see text]GHz and a gain of 29[Formula: see text]dB is accomplished. A 2[Formula: see text]pF load capacitance can be driven at a phase margin of [Formula: see text]. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40[Formula: see text][Formula: see text]m layout area and ultra-wide 3-dB bandwidth.

Gain-Based Double Feedforward Compensation for Multi-Stage Amplifiers

A gain-based double feedforward compensation (GBDFC) for multi-stage amplifiers is proposed, which could be used in multi-stage OTA design. The proposed compensation technique provides two left-plane zeros to counteract with the first and second non-dominant poles of the OTA without reducing the dominant pole obviously. Meanwhile, a high slew-rate is presented in the condition of large step input signal. A three-stage Opamp prototype with the proposed technique is realized in a 0.18 yitm CMOS process. The post simulation results show that it provides a unity-gain bandwidth (GBW) of 103 MHz and phase margin (PM) of 70° with power consumption of 0.328 mW and small compensation capacitors, implying a better FOM compare with the state-of-the-art.

A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction

A fully integrated high efficiency switched-capacitor (SC) DC-DC converter with pulse frequency modulation (PFM) control is presented. The small signal model of the multiphase-interleaving SC converter is given and it is verified through the simulation and the measurement results. For high efficiency, this design set the dominant pole at the output of the error amplifier (EA) and the 14-phase interleaving topology can push the non-dominant pole away from the Unit Gain Frequency (UGF) for the loop stability. By combining the flying-well and the deep n-well (DNW) isolation techniques, the proposed high-density MOS capacitor can reduce both the parasitic loss and the charge sharing loss of the converter. The conversion ratio of the converter is 2:1 under 3.3V power supply. This SC DC-DC converter is fabricated in the 40 nm CMOS process. It obtains the peak efficiency of 86.2% and the output power-density of 226 mW/mm2. It maintains the efficiency above 80% from 8 mA to 50 mA load condition.

An Improved Analytical Tuning Rule of a Robust PID Controller for Integrating Systems with Time Delay Based on the Multiple Dominant Pole-Placement Method

An improved analytical tuning rule of a Proportional-Integral-Derivative (PID) controller for integrating systems with time delay is proposed using the direct synthesis method and multiple dominant pole-placement approach. Different from the traditional multiple dominant pole-placement method, the desired characteristic equation is obtained by placing the third-order dominant poles at −1/λ and placing the second-order non-dominant poles at −5/λ (λ is the tuning parameter). According to root locus theory, the third-order dominant poles and the second-order non-dominant poles are nearly symmetrically located at the two sides of the fifth-order dominant poles. This makes the third-order dominant poles closer to the imaginary axis than the fifth-order dominant poles, which means that, possibly, better performances can be achieved. Analytical formulas of a PID controller with a lead-lag filter are derived. Simple tuning rules are also given to achieve the desired robustness, which is measured by the maximum sensitivity (Ms) value. The proposed method can achieve better performances and maintain better performances when there exist parameters’ perturbation compared with other methods. Simulations for various integrating processes as well as the nonlinear continuous stirred tank reactor (CSTR) model illustrate the applicability and effectiveness of the proposed method.

Capacitor‐less FVF low drop‐out regulator with active feed‐forward compensation and efficient slew‐rate enhancer circuit

In this study, an improved capacitor-less flipped voltage follower (FVF) low drop-out regulator (LDO) with active feed-forward compensation (AFFC) and an efficient slew-rate enhancer (SRE) circuit is presented. In capacitor-less FVF LDOs, the dominant pole is placed at the gate of the power metal oxide semiconductor field effect transistor (MOSFET) which demands minimum load current for the feedback-loop to be stable. The proposed compensator has miller compensation along with AFFC which helps to eliminate the minimum load demand for the feedback-loop of the LDO to be stable by shifting the right half-plane (RHP) zero of power MOSFET to left half-plane (LHP) zero. This LHP zero proportionally varies with the first non-dominant pole at the output of the LDO as the load current varies from light load to heavy load and extends the unity gain frequency of the proposed LDO. The SRE circuit supports fast load transients with edge time of 50 ns and achieves less voltage spike without consuming any power at steady-state. This LDO is implemented in 0.18 μ m technology with a drop-out voltage of 200 mV and can drive the load current range of 0–50 mA with regulated output voltages from 1.2 to 1.6 V. It settles faster with the settling time of 250 ns and has the quiescent current of 25.8 μ A .

Low-Power Area-Efficient LDO With Loop-Gain and Bandwidth Enhancement Using Non-Dominant Pole Movement Technique for IoT Applications

A new Low Drop-Out (LDO) voltage regulator with off-chip capacitor for low power applications is presented. The LDO takes advantage of non-dominant pole movement technique to improve loop-gain and Unity Gain Frequency (UGF). Tangible improvements were obtained while supporting a large load capacitor and low-power consumption. The proposed LDO 1) consumes low quiescent current (47.3% current efficiency (CE) at 10 μA load current bias circuit inclusive), 2) is area-efficient (no multi-gain amplifiers), and 3) enjoys a short response time in the active-mode with its adaptive bandwidth expansion and loop-gain enhancement technique, while 4) maintaining 99.94% CE in the full-load condition. A prototype chip with TSMC 180 nm CMOS technology was fabricated for detailed characterisation. The measured output voltage of the LDO was 1.65 V with 1.8 V input, consuming 11 μA quiescent current including the bias circuit current. The load regulation was 10 mV when load current changes from 30 nA to 50 mA with fall and rise time of 10ns.

A High Current Efficiency Two-Stage Amplifier With Inner Feedforward Path Compensation Technique

A high current efficiency two-stage amplifier with inner feedforward path compensation (IFPC) technique is proposed in this paper. To improve the current utilization of the whole structure, the recycling folded cascode amplifier (RFC) is adopted as the first stage, and the inner feedforward path which is used to eliminate the non-dominant pole is composed of the input stage of RFC and the tail current transistor of the second stage amplifier. By using the IFPC technique, the proposed amplifier achieves an extended gain-bandwidth (GBW) and sufficient phase margin (PM) compared to that of the two-stage amplifier using single Miller compensation (SMC). Moreover, this compensation technique avoids extra power consumption since it does not require additional circuits. The proposed two-stage IFPC amplifier was fabricated in a $0.18~\mu \text{m}$ CMOS technology and the chip area of it is about $0.076mm^{2}$ . The simulated open loop AC response shows the DC gain, GBW, and PM are 130dB, 2.01MHz, and 58.3°, respectively. Measured results of transient response show when driving a 120pF load capacitance, the proposed amplifier achieves 368ns average 1% settling time, and about 1.56V/ $\mu \text{s}$ average slew rate (SR). Note that under the condition of 1.8V power supply, the power consumption is only $108\mu W$ , proving the proposed two-stage IFPC amplifier can achieve high current efficiency while maintaining stability.