Nondestructive Readout Operation Research Articles

Effect of ferroelectric and interface films on the tunneling electroresistance of the Al2O3/Hf0.5Zr0.5O2 based ferroelectric tunnel junctions

Ferroelectric random-access memory (FRAM) based on conventional ferroelectric materials is a non-volatile memory with fast read/write operations, high endurance, and 10 years of data retention time. However, it suffers from destructive read-out operation and lack of CMOS compatibility. HfO2-based ferroelectric tunnel junctions (FTJ) may compensate for the shortcomings of FRAM by its CMOS compatibility, fast operation speed, and non-destructive readout operation. In this study, we investigate the effect of ferroelectric and interface film thickness on the tunneling electroresistance or ON/OFF current ratio of the Hf0.5Zr0.5O2/Al2O3 based FTJ device. Integrating a thick ferroelectric layer (i.e. 12 nm Hf0.5Zr0.5O2) with a thin interface layer (i.e. 1 nm Al2O3) resulted in an ON/OFF current ratio of 78. Furthermore, to elucidate the relationship between ON/OFF current ratio and interfacial properties, the Hf0.5Zr0.5O2-Al2O3 films and Ge-Al2O3 interfaces are examined via time-of-flight secondary ion mass spectrometry depth profiling mode. A bilayer oxide heterostructure (Hf0.5Zr0.5O2/Al2O3) is deposited by atomic layer deposition (ALD) on the Ge substrate. The ON/OFF current ratio is enhanced by an order of magnitude when the Hf0.5Zr0.5O2 film deposition mode is changed from exposure (H2O) ALD to sequential plasma (sequential O2–H2) ALD. Moreover, the interfacial engineering approach based on the in situ ALD H2-plasma surface pre-treatment of Ge increases the ON/OFF current ratio from 9 to 38 by reducing the interfacial trap density state at the Ge-Al2O3 interface and producing Al2O3 with fewer oxygen vacancies as compared to the wet etch (HF + H2O rinse) treatment of the Ge substrate. This study provides evidence of strong coupling between Hf0.5Zr0.5O2 and Al2O3 films in controlling the ON/OFF current ratio of the FTJ.

Data retention and low voltage operation of Al2O3/Hf0.5Zr0.5O2 based ferroelectric tunnel junctions

Ferroelectric random-access memories based on conventional perovskite materials are non-volatile but suffer from lack of CMOS compatibility, scalability limitation, and a destructive reading scheme. On the other hand, ferroelectric tunnel junctions based on CMOS compatible hafnium oxide are a promising candidate for future non-volatile memory technology due to their simple structure, scalability, low power consumption, high operation speed, and non-destructive read-out operation. Herein, we report an efficient strategy based on the interface-engineering approach to improve upon the tunneling electroresistance effect and data retention by depositing bilayer oxide heterostructure (Al2O3/Hf0.5Zr0.5O2) using atomic layer deposition (ALD) on Ge substrate which is treated in-situ ALD chamber with H2-plasma before film deposition. Integrating a thin ferroelectric layer i.e. Hf0.5Zr0.5O2 (8.4 nm) with a thin interface layer i.e. Al2O3 (1 nm) allowed us to reduce the operation (read and write) voltage to 1.4 V, and 4.3 V, respectively, while maintaining a good tunneling electroresistance or ON/OFF ratio above 10. Furthermore, an extrapolation to 1000 years at room temperature gives a residual ON/OFF ratio of 4.

Low-energy complementary ferroelectric-nanocrack logic

Abstract Ferroelectric-based electronic devices have excellent low-energy characteristics due to the highly insulating property, in which the Joule heating can be neglected. The recent discovery of electrically switchable cracks in ferroelectric/alloy film heterostructure gave rise to a new way to construct transistor, where the opening and closing of crack switched the channel current off and on. Here, we observed the complementary switching of cracks for the first time, and demonstrated a complementary inverter without any additional process to set different types of transistors, which was implemented by forming the n- and p-type transistor in conventional complementary metal oxide semiconductor (CMOS) technology. The complementary states were generated spontaneously once the cracks were induced and varied with the change of applied input voltage polarity. The low ON resistance and near-zero OFF state leakage current result in the high current on/off ratio (~107) and allow for the low dynamic and static power dissipation. Further, the switching of cracks is coupled to the surrounding ferroelectric polarization states, offering the non-destructive readout operation. We believe that our work provides a very simple route to build complementary logic gates and paves a way for the energy-efficient electronic devices, while promoting the “crack nanoelectronics”.

Nonvolatile Photoelectric Memory Induced by Interfacial Charge at a Ferroelectric PZT‐Gated Black Phosphorus Transistor

AbstractFerroelectric‐field‐effect‐transistor (FeFET) memory, characterized by its nonvolatile, nondestructive readout operation and low power consumption, has attracted tremendous attention in the development of next‐generation random‐access memory. However, the electrical reading processes in conventional FeFETs may attenuate the ferroelectric (FE) polarization and lead to readout crosstalk. A photoelectric‐type FeFET memory with alternative readout through 2D black phosphorus (BP)/lead zirconate titanate (PZT) heterostructures is developed. Based on charge‐mediated electric‐field control, a unique polarization‐dependent photoresponse is observed, resulting in both positive photoconductivity (PPC) and negative photoconductivity (NPC) in a single device element via FE gating. This enables a nonvolatile photoelectric memory working in a novel “electrical writing‐optical reading” process mode. Furthermore, the device exhibits a reliable data retention (over 3.6 × 103 s) and fatigue (exceeding 500 cycles) performance with extremely low energy consumption (driving voltage <10 mV). The demonstrated BP/PZT heterostructure memory devices show a pathway to high‐performance photoelectric storage devices as light‐activated logic gates for on‐chip optical communications.

Back-to-back Interface diodes induced symmetrical negative differential resistance and reversible bipolar resistive switching in β-CuSCN trigonal pyramid micro/nanoarray

As a superior p-type wide bandgap semiconductor, β-CuSCN has a huge potential in optoelectronic device application, and however its conduction could intensively be affected by externally applied bias. Here, we demonstrate electrodeposited individual β-CuSCN trigonal micro/nanopyramids and their array films can show Cu+ trap-controlled bias dependence of electron transport. Before being subjected to a large reverse bias or a unidirectional bias, their cyclic IV curves are coincident resulted from bulk-trap related carrier hopping. At relatively large bidirectional operation bias, they can symmetrically present two large hysteresis loops with negative differential resistance (NDR), and meanwhile accompany with nonvolatile negative resistive switching (RS) feature. After being applied respectively a relatively large fixed bias in two opposite directions, more importantly, switchable classic asymmetrical bipolar RS can successfully be realized at a relatively low operation bias. The switchable formation of reversion and depletion layer, resulted from the minority carriers (electrons) injection into the traps of surface connected with negative electrode, plays a crucial role. Under relatively large bias, the synergistic effect of two surface trap-related back-to-back connected bipolar RS devices results in symmetrical negative RS with NDR. After being applied a relatively large fixed bias, the bipolar RS effect can be enhanced at the surface connected with negative electrode due to the presence of electron injection induced high and narrow barrier, and conversely it disappears at the surface connected with positive electrode due to hole injection-induced ohmic contact. Then, the devices can be set and reset by the filling and emptying of holes in the thin reversion and depletion layer at low reverse and forward voltages, respectively, showing switchable bipolar RS behavior. Due to superior stability, reversibility, nondestructive readout, and low operation bias as well as remarkable cycle performance, the bias-governed conduction with negative RS and switchable bipolar RS makes it a potential candidate in next-generation erasable nonvolatile RRAM devices.

One-Transistor-One-Transistor (1T1T) Optoelectronic Nonvolatile MoS2 Memory Cell with Nondestructive Read-Out.

Taking advantage of the superlative optoelectronic properties of single-layer MoS2, we developed a one-transistor-one-transistor (1T1T)-type MoS2 optoelectronic nonvolatile memory cell. The 1T1T memory cell consisted of a control transistor (CT) and a memory transistor (MT), in which the drain electrode of the MT was connected electrically to the gate electrode of the CT, whereas the source electrode of the CT was connected electrically to the gate electrode of the MT. Single-layer MoS2 films were utilized as the channel materials in both transistors, and gold nanoparticles acted as the floating gates in the MT. This 1T1T device architecture allowed for a nondestructive read-out operation in the memory because the writing (programming or erasing) and read-out processes were operated separately. The switching of the CT could be controlled by light illumination as well as the applied gate voltage due to the strong light absorption induced by the direct band gap of single-layer MoS2 (∼1.8 eV). The resulting MoS2 1T1T memory cell exhibited excellent memory performance, including a large programming/erasing current ratio (over 106), multilevel data storage (over 6 levels), cyclic endurance (200 cycles), and stable retention (103 s).

Predicting a ferrimagnetic phase of Zn(2)FeOsO(6) with strong magnetoelectric coupling.

Multiferroic materials, in which ferroelectric and magnetic ordering coexist, are of practical interest for the development of novel memory devices that allow for electrical writing and nondestructive magnetic readout operation. The great challenge is to create room temperature multiferroic materials with strongly coupled ferroelectric and ferromagnetic (or ferrimagnetic) orderings. BiFeO_{3} is the most heavily investigated single-phase multiferroic to date due to the coexistence of its magnetic order and ferroelectric order at room temperature. However, there is no net magnetic moment in the cycloidal (antiferromagneticlike) magnetic state of bulk BiFeO_{3}, which severely limits its realistic applications in electric field controlled memory devices. Here, we predict that LiNbO_{3}-type Zn_{2}FeOsO_{6} is a new multiferroic with properties superior to BiFeO_{3}. First, there are strong ferroelectricity and strong ferrimagnetism at room temperature in Zn_{2}FeOsO_{6}. Second, the easy plane of the spontaneous magnetization can be switched by an external electric field, evidencing the strong magnetoelectric coupling existing in this system. Our results suggest that ferrimagnetic 3d-5d LiNbO_{3}-type material may therefore be used to achieve voltage control of magnetism in future memory devices.

Selective remanent ambipolar charge transport in polymeric field-effect transistors for high-performance logic circuits fabricated in ambient.

Ambipolar polymeric field-effect transistors can be programmed into a p- or n-type mode by using the remanent polarization of a ferroelectric gate insulator. Due to the remanent polarity, the device architecture is suited as a building block in complementary logic circuits and in CMOS-compatible memory cells for non-destructive read-out operations.

Room-temperature spin-spiral multiferroicity in high-pressure cupric oxide

Multiferroic materials, in which ferroelectric and magnetic ordering coexist, are of fundamental interest for the development of multi-state memory devices that allow for electrical writing and non-destructive magnetic read-out operation. The great challenge is to create multiferroic materials that operate at room-temperature and have a large ferroelectric polarization P. Cupric oxide, CuO, is promising because it exhibits a significant polarization, i.e. P ~ 0.1 μC.cm−2, for a spin-spiral multiferroic. Unfortunately CuO is only ferroelectric in a temperature range of 20 K, from 210 to 230 K. Here, using a combination of density functional theory and Monte Carlo calculations, we establish that pressure-driven phase competition induces a giant stabilization of the multiferroic phase of CuO, which at 20-40 GPa becomes stable in a domain larger than 300 K, from 0 to T > 300 K. Thus, under high-pressure, CuO is predicted to be a room-temperature multiferroic with large polarization.

High-κ Insulator Thin Films and Retention Properties of MFIS Diodes

ABSTRACTFerroelectric field effect transistor (FFET) is a promising candidate for non-volatile random access memory because of its high speed, single device structure, low power consumption, and nondestructive read-out operation. Currently, however, such ideal devices are commercially not available due to poor interface properties between ferroelectric film and Si substrate, such as leakage current and interdiffusion etc. So we choose YSZ and HfO2 insulating thin films as buffer layer due to they possess relatively high dielectric constant, high thermal stability, low leakage current, and good interface property with Si substrates. Two structural diodes of Pt/BNT/YSZ/Si and Pt/SBT/HfO2/Si were fabricated, and the microstructures, interface properties, C-V, I-V, and retention properties were investigated in detail. Experimental results show that the fabricated diodes exhibit excellent long-term retention properties, which is due to the good interface and the low leakage density, demonstrating that the YSZ and HfO2 buffer layers are playing a critical modulation role between the ferroelectric thin film and Si substrate.

Nondestructive Readout Operation of Oxide-Thin-Film-Transistor-Based 2T-Type Nonvolatile Memory Cell

A two-transistor-type nonvolatile memory cell composed of one-access and one-memory thin-film transistors (TFTs) was demonstrated. ZnO and poly(vinylidene fluoride-trifluoroethylene) were employed as semiconducting channels for both TFTs and ferroelectric-gate insulator for memory TFT, respectively, in which the cell structures and fabrication procedures were so carefully designed and optimized as to effectively incorporate both TFTs on the same glass substrate without any critical process damage even below 200°C. The fabricated memory cell successfully showed the write and nondestructive readout operations.

Overview and Future Challenge of Ferroelectric Random Access Memory Technologies

We have developed a low-temperature formation technique for ferroelectrics (<500 °C), which is crucial for the ferroelectric random access memory (FeRAM) to be embedded in a leading-edge complementary metal oxide semiconductor (CMOS). A 53-nm-thick Bi4Ti3O12 film was successfully formed by metalorganic chemical vapor deposition at 450 °C and subsequent annealing at 500 °C. It was found that perovskite grains preferentially orient along the (110) and (111) directions and that the fabricated Bi4Ti3O12 capacitors show a remnant polarization (2Pr) of as large as 25.7 µC/cm2. In addition, we have adopted a nondestructive readout operation (NDRO) technique to extend read cycle endurance, in which the switched polarization at reading is automatically rewritten by readout voltage removal. We have demonstrated stable readout characteristics at more than 1011 cycles for 0.18 µm NDRO FeRAMs.

IMPROVEMENT IN NON-DESTRUCTIVE READOUT RELIABILITY OF FERAM WITH ASYMMETRICAL PROGRAMMING

ABSTRACT A nondestructive readout (NDRO) scheme without polarization reversal in a ferroelectric random access memory (FeRAM) is proposed as a solution for extending the number of readout cycles. However, the readout signal in an NDRO FeRAM is so small that the NDRO operation is sensitive to deformation of the P−V hysteresis loop, which is a manifestation of imprint phenomena. In order to minimize the imprint effect in the NDRO FeRAM, we introduced an asymmetrical polarization programming scheme. Using this scheme, we can expect an extended number of readout cycles more than 1016 regardless of the imprint phenomena in ferroelectric capacitors.

0.18-&amp;lt;tex&amp;gt;$muhboxm$&amp;lt;/tex&amp;gt;Nondestructive Readout FeRAM Using Charge Compensation Technique

A nondestructive readout (NDRO) FeRAM using a 0.18-/spl mu/m CMOS technology has been developed. Readout voltages across the ferroelectric lower than the coercive voltage allowed the FeRAM to achieve high read endurance exceeding required performance for system LSIs, 10/sup 16/ read cycles. The NDRO approach uses a newly developed charge compensation technique to correct the process variations in threshold voltage of neighboring readout transistors, leading to a wide NDRO operation margin over a supply voltage range from 1.1 to 1.8 V.

Current Status of Ferroelectric Random-Access Memory

AbstractThe current status of ferroelectric random-access memory (FeRAM) technology is reviewed in this article. Presented first is the status of conventional FeRAM, in which the memory cells are composed of ferroelectric capacitors to store the data and cell-selection transistors to access the selected capacitors. Discussed next are recent developments in the field. Pb(Zrx, Ti1–x)O3 (PZT) and SrBi2Ta2O9 (SBT) films are being used to produce 0.13 mμ and 0.18 μm FeRAM cells, respectively, with a stacked capacitor configuration; these cells are easily embedded into logic circuits. A new class of FeRAM called 6T4C—containing static RAM (SRAM) cells composed of six transistors (6T) and four ferroelectric capacitors (4C)—has been commercially produced. This type of FeRAM features a nondestructive readout operation, unlimited read/write cycling, and a fast access time of less than 10 ns. Lastly, the status of field-effect-transistor (FET)-type FeRAM is reviewed, emphasizing that the data retention time of a ferroelectric-gate FET has been improved to more than a month in recent studies.

High-speed test of SFQ-shift register files using PTL wiring

We have been developing an SFQ shift register memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift register memory is composed of shift registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the memory system at high speed. The tested circuit is a 4-byte shift register file, where four kinds of wiring circuits are used between a decoder and shift registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the memory system. We have used the NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library.

Noise characteristics of stacked CMOS active pixel sensor for charged particles

The noise characteristics of a stacked CMOS active pixel sensor (SCAPS) for incident charged particles have been analyzed under 4.5 keV Si + ion irradiation. The source of SCAPS dark current was found to change from thermal to electron leakage with decreasing device temperature. Leakage current at charge integration part in a pixel has been reduced to 0.1 electrons s −1 at 77 K. The incident ion signals are computed by subtracting reset frame values from each frame using a non-destructive readout operation. With increase of irradiated ions, the dominant noise source changed from read noise, and shot noise from the incident ions, to signal frame fixed-pattern noise from variations in sensitivity between pixels. Pixel read noise is equivalent to ten incident ions. The charge of an incident ion is converted to 1.5 electrons in the pixel capacitor. Shot noise corresponds to the statistical fluctuation of incident ions. Signal frame fixed-pattern noise is 0.7% of the signal. By comparing full well conditions to noise floor, a dynamic range of 80 dB is achieved. SCPAS is useful as a two-dimensional detector for microanalyses such as stigmatic secondary ion mass spectrometry.

Memory characteristics of Au/PZT/BIT/p-Si ferroelectric diode

A ferroelectric memory diode consisting of Au/PZT/BIT/p-Si multilayer configuration has been fabricated by pulsed laser deposition (PLD) technique. The ferroelectric properties and the memory characteristics are investigated. The P-E curve of the PZT/BIT/p-Si films system had an asymmetry saturated hysteresis loop withP t=15 μC/cm2 andE c=48 kV/cm, and the decay in remanent polarization was only 10% after 109 switching cycles, meanwhile the increase in coercive field was 12%. The C-V hysteresis loop and the I-V curve showed a memory effect derived from the ferroelectric polarization of PZT/BIT films, and the current density was 6.7×10−8 A/cm2 at a voltage of +4V. Our diode had nonvolatile and nondestructive memory readout operation. There was a read current disparity of 0.05 μA for logic “1” and logic “0” at a read voltage of +2V, and the stored logical value (“1” or “0”) could be read out in 30 min.

Nondestructive readout of photochromic optical memory using photocurrent detection

We proposed and demonstrated a nondestructive readout method using photocurrent detection for photon-mode photochromic memory. The principle of this readout method, which utilized the ionization potential change according to photoisomerzation reaction, was confirmed by using a medium with a photochromic diarylethene layer and phthalocyanine photoabsorbing layer, and by using a near-infrared readout light. We demonstrated perfect nondestructive readout operations over 106 times.

Fabrication and characteristics of Au/PZT/BIT/p-Si ferroelectric memory diode

A ferroelectric memory diode that consisted of Au/PZT/BIT/p-Si multilayer configuration was fabricated. The Pb(Zr 0.52Ti 0.48)O 3 (PZT) ferroelectric films with a c-axis oriented Bi 4Ti 3O 12 (BIT) buffer layer were deposited on a p-Si(1 0 0) substrate by pulsed laser deposition technique. The ferroelectric characteristics and the electrical characteristics were measured respectively. The results suggested that the growth of the BIT ferroelectric layer was helpful to increase the memory window and to reduce the current density by impairing the serious interaction and interdiffusion at the ferroelectric/Si interface. The C–V hysteresis loop showed a memory effect due to the ferroelectric polarization of PZT/BIT films. The I–V curve was Schottky-diode-like and had a hysteresis loop due to the ferroelectric remanent polarization. We confirmed our diode had nonvolatile and nondestructive memory readout operation. After applied a writing voltage of +5 V for logic “1” and −5 V for logic “0” respectively, the reading currents were 0.1 and 0.05 μA at a reading voltage of +2 V correspondingly.