Non-binary LDPC Codes Research Articles

Efficient information reconciliation for high-dimensional quantum key distribution

The information reconciliation phase in quantum key distribution has significant impact on the range and throughput of any QKD system. We explore this stage for high-dimensional QKD implementations and introduce two novel methods for reconciliation. The methods are based on nonbinary LDPC codes and the Cascade algorithm, respectively, and achieve efficiencies close the Slepian–Wolf bound on q-ary symmetric channels.

Minimum-Set Min-Sum Decoding Algorithms for Non-Binary LDPC Codes

Minimum-Set Min-Sum Decoding Algorithms for Non-Binary LDPC Codes

A Low-Complexity Bit-Embedding Decoder for Non-Binary LDPC Codes in $\mathbb {F}_{2^{q}}$

A Low-Complexity Bit-Embedding Decoder for Non-Binary LDPC Codes in $\mathbb {F}_{2^{q}}$

Momentum-Based Symbol Flipping Decoding Algorithms for Non-Binary LDPC Codes

This paper investigates the application of gradient descent with momentum in symbol flipping decoding algorithms based on prediction (SFDP) for non-binary low-density parity-check (NB-LDPC) codes. The momentum added in the objective function of SFDP algorithms can provide inertia to the decoding process by considering the flipping states in the past iterations. Simulation results show that the proposed momentum-based SFDP algorithms perform significantly better than the original SFDP algorithms with low extra complexity. Furthermore, to lower the error floor of momentum-based SFDP algorithms, we also introduce artificial noises into the objective functions of momentum-based SFDP algorithms to help the iterative decoding escape from local optimum.

Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder

Limitations on hardware resource consumption and throughput make the use of non-binary low-density parity-check (NB-LDPC) codes challenging in practical applications. This paper first proposes a novel check-node (CN) decoding algorithm called Hamming-distance trellis min-max (H-TMM) to reduce the complexity introduced by searching for two minimum values in previous TMM-based algorithms. Then, by taking advantage of the proposed algorithm and the number appearances of reliable values, a high-performance H-TMM-based NB-LDPC decoder architecture is presented. Experiments on the 32-ary (837, 726) NB-LDPC code confirmed that the proposed decoder can obtain a high throughput on less hardware resources compared with the state-of-the-art works while maintaining a competitive error-correcting performance. In particular, the proposed CN unit architecture reduced hardware resources by almost half compared to that in the latest decoder.

Trapping and Absorbing Set Enumerators for Irregular Generalized Low-Density Parity-Check Code Ensembles

The definitions of (elementary) trapping and (fully) absorbing sets are extended to generalized low-density parity-check (GLDPC) codes. In particular, the fully absorbing sets are stable under the bit flipping algorithm. The finite-length (elementary) trapping and (fully) absorbing set enumerators for unstructured irregular GLDPC code ensembles are derived using generating functions. An efficient method to evaluate the asymptotic trapping and (fully) absorbing set distributions is presented, which requires solving a system of equations. Using this method, the asymptotic distribution of trapping and (fully) absorbing sets are evaluated for some example GLDPC code ensembles. Experimental results show that the proposed definitions yield graph structures that are harmful for bit flipping decoders. The generating function approach is also used to derive the finite-length and asymptotic trapping and (elementary) absorbing set enumerators for non-binary irregular LDPC code ensembles.

Trapping and Absorbing Set Enumerators for Nonbinary Protograph-Based Low-Density Parity-Check Code Ensembles

The finite-length trapping and (elementary) absorbing set enumerators for nonbinary protograph-based LDPC code ensembles are derived. Both constrained and unconstrained edge labeling approaches are considered. The normalized logarithmic asymptotic distributions of trapping and (elementary) absorbing sets are obtained through an efficient method that requires solving a system of equations. Using these results, the asymptotic distributions of trapping and (elementary) absorbing sets are evaluated for some example nonbinary protograph-based LDPC code ensembles.

An Adaptive Single/Multiple Symbol Flipping Decoding Algorithm for Non-Binary LDPC Codes

This letter presents an adaptive single/multiple distance-symbol flipping decoding algorithm with prediction (ASMD-SFDP). Different from the D-SFDP, the presented algorithm consider both the global maximization and sec-maximization values of the reliability fluctuation quantity (RFQ). Flipping operation is performed only when the global maximization is greater than or equal to zero. Furthermore, a new flipping strategy is introduced based on the numerical gap between the global maximization and sec-maximization. The flipping operation is performed adaptively: 1) If the gap is greater than or equal to a designed threshold, only single symbol is flipped; 2) Otherwise, multiple symbols are flipped. Simulation results show that the presented algorithm can achieve a significant performance gain of 0.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 0.5 dB compared with the original D-SFDP algorithm. More interestingly, the presented algorithm also shows a much faster convergence speed.

Symbol-Level Detection With Matched Non-Binary LDPC Codes for Position Errors in Racetrack Memories

In racetrack memory (RM), insertion and deletion (ID) errors occur owing to alignment faults; such errors are referred to as position errors (PEs). Recently, several coding schemes for PEs have been proposed based on binary low-density parity-check (BI-LDPC) codes with a joint bit-wise (BW) detection and decoding algorithm. Although these schemes yield promising asymptotic performance, they suffer from unsatisfactory finite-length performance in short block sizes. To address this problem, we propose a novel coding scheme based on non-binary LDPC (NB-LDPC) codes and symbol-wise (SW) detection. The factor graph of the proposed scheme avoids generating cycles between the detector and decoder graphs by leveraging RM’s special property that multiple ID errors are caused by PEs simultaneously, which enables the attainment of good finite-length performance while providing fast convergence. With the aim of providing further performance improvement, we also provide an SW extrinsic information transfer chart analysis to design NB-LDPC codes for the proposed scheme.

Concatenated Codes for Multiple Reads of a DNA Sequence

Decoding sequences that stem from multiple transmissions of a codeword over an insertion, deletion, and substitution channel is a critical component of efficient deoxyribonucleic acid (DNA) data storage systems. In this paper, we consider a concatenated coding scheme with an outer nonbinary low-density parity-check code or a polar code and either an inner convolutional code or a time-varying block code. We propose two novel decoding algorithms for inference from multiple received sequences, both combining the inner code and channel to a joint hidden Markov model to infer symbolwise a posteriori probabilities (APPs). The first decoder computes the exact APPs by jointly decoding the received sequences, whereas the second decoder approximates the APPs by combining the results of separately decoded received sequences and has a complexity that is linear with the number of sequences. Using the proposed algorithms, we evaluate the performance of decoding multiple received sequences by means of achievable information rates and Monte-Carlo simulations. We show significant performance gains compared to a single received sequence. In addition, we succeed in improving the performance of the aforementioned coding scheme by optimizing both the inner and outer codes.

-Ary Distributed Arithmetic Coding for Uniform -Ary Sources

Laplacian distribution is widely used to model the differences between correlated continuous or nonbinary signals, e.g., the predictive residues of videos. Usually, distributed coding of correlated nonbinary sources, e.g., distributed video coding, is implemented by binary or nonbinary Low-Density Parity-Check (LDPC) codes. In this paper, as an alternative, we attempt using nonbinary Distributed Arithmetic Coding (DAC) to implement distributed coding of uniform nonbinary sources with Laplace-distributed correlation. To analyze <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -ary DAC for uniform <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -ary sources, following the methodology developed in our prior work for binary DAC, we define and deduce Coset Cardinality Spectrum (CCS) from both fixed-length and variable-length perspectives, whose physical meanings are explained in detail; while for binary DAC, our prior work totally ignored the subtle difference between these two perspectives. Compared with binary DAC, an important advantage of nonbinary DAC is that, the mapping from source symbols to coding intervals is so flexible that there are many parameters that can be tuned to achieve better performance; while for binary DAC, there are very few tunable parameters, making it very hard to achieve better performance. This paper proposes a simple method to map source symbols onto coding intervals, which results in a very lightweight codec, while possessing a good Manhattan distance distribution. Then this paper deduces the formula of path metrics for decoder design by making use of CCS. All theoretical analyses are perfectly verified by simulation results. Most important, experimental results show that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -ary DAC achieves significantly better performance than LDPC codes for distributed coding of uniform <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -ary sources with Laplace-distributed correlation.

Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension

The Consultative Committee for Space Data Systems (CCSDS) recommends the use of short-block length Bose-Chaudhuri-Hocquenghem (BCH) and binary low-density parity-check (LDPC) codes. Despite the high error-correction capacity of non-binary low-density parity-check (NB-LDPC) codes, they have not yet been considered due to their high decoding complexity. In this paper, the feasibility of NB-LDPC coding for space telecommand link applications using a RISC-V soft-core processor plus a vector co-processor is demonstrated. The purpose of this work is to avoid the need for a dedicated decoder hardware, and thus the customized general-purpose processor which performs decoding can be reconfigured to perform other important on-board tasks. In this way, the logic utilization and power consumption can be reduced since more functionalities can be assumed by the on-board processor. The method of acceleration of a NB-LDPC decoder over GF(16) using the RISC-V vector extension is demonstrated, and a throughput of 8.48 kbps is achieved for the Forward-Backward implementation of the min-max decoding algorithm, which is compatible with the low-rate and mid-rate telecommand systems recommended by CCSDS.

Data postprocessing for the one-way heterodyne protocol under composable finite-size security

The performance of a practical continuous-variable (CV) quantum key distribution (QKD) protocol depends significantly, apart from the loss and noise of the quantum channel, on the post-processing steps which lead to the extraction of the final secret key. A critical step is the reconciliation process, especially when one assumes finite-size effects in a composable framework. Here, we focus on the Gaussian-modulated coherent-state protocol with heterodyne detection in a high signal-to-noise ratio regime. We simulate the quantum communication process and we post-process the output data by applying parameter estimation, error correction (using high-rate, non-binary low-density parity-check codes), and privacy amplification. This allows us to study the performance for practical implementations of the protocol and optimize the parameters connected to the steps above. We also present an associated Python library performing the steps above.

LDPC Codes Over GF(q) With Alterable Subset for PAPR Reduction in OFDM Systems

Non-binary low-density parity-check (NB-LDPC) codes can exhibit more considerable coding gain than their binary counterparts in numerous cases. To further exploit the benefit of NB-LDPC codes, in this letter, a novel type of non-binary LDPC codes, alterable subset non-binary LDPC (AS-NB-LDPC) codes, is proposed for reducing the peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) systems. Firstly, we design the alteration scheme of AS-NB-LDPC codes to make <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> -ary LDPC codes generate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> valid codewords through one alterable subset, and the codeword with the minimum PAPR is selected for transmission. Then inspired by the invertible subset for binary LDPC codes, the necessary and sufficient conditions for alterable subset generation are derived. Furthermore, we propose an improved progressive edge growth (PEG) construction method to obtain AS-NB-LDPC codes with favorable frame error rate (FER) performance. Simulation results verify the effectiveness of the proposed NB-LDPC codes.

High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm

Providing superior algorithm-level performance, the non-binary low-density parity-check (NB-LDPC) code is now expected to be one of the next-generation error-correction codes. However, it is hard to implement a high-throughput NB-LDPC decoder in practice due to its impractical processing complexity and the excessively long decoding time. Based on the previous extended min-sum (EMS) approach, in this work, we introduce the parallel EMS (pEMS) decoding algorithm that reduces the processing latency of each iteration by managing multiple message entries at a time. The previous two-phase node-level operation is modified to promote the proposed parallel processing without performance degradation, where the delay overheads are minimized by carefully optimizing the internal sorters with input attributes. In addition, the data accessing sequence is precisely adjusted to reduce the number of waiting cycles, further increasing the overall processing efficiency. Implemented in a 22-nm FinFET technology, as a result, the prototype two-parallel decoder for (160, 80) NB-LDPC codes operates at the speed of 950 MHz, achieving the decoding throughput of more than 7 Gb/s, which is 3.2 times faster than the state-of-the-art design.

Decoding Nonbinary LDPC Codes via Proximal-ADMM Approach

In this paper, we focus on decoding nonbinary low-density parity-check (LDPC) codes in Galois fields of characteristic two via the proximal alternating direction method of multipliers (proximal-ADMM). By exploiting Flanagan/Constant-Weighting embedding techniques and the decomposition technique based on three-variables parity-check equations, two efficient proximal-ADMM decoders for nonbinary LDPC codes are proposed. We show that both of them are theoretically guaranteed convergent to some stationary point of the decoding model and either of their computational complexities in each proximal-ADMM iteration scales linearly with LDPC code’s length and the size of the considered Galois field. Moreover, the decoder based on the Constant-Weight embedding technique satisfies the favorable property of codeword symmetry. Simulation results demonstrate their effectiveness in comparison with state-of-the-art LDPC decoders.

GF(q) LDPC encoder and decoder FPGA implementation using group shuffled belief propagation algorithm

This paper presents field programmable gate array (FPGA) exercises of the GF(q) low-density parity-check (LDPC) encoder and interpreter utilizing the group shuffled belief propagation (GSBP) algorithm are presented in this study. For small blocks, non-dual LDPC codes have been shown to have a greater error correction rate than dual codes. The reduction behavior of non-binary LDPC codes over GF (16) (also known as GF(q)-LDPC codes) over the additive white Gaussian noise (AWGN) channel has been demonstrated to be close to the Shannon limit and employs a short block length (N=600 bits). At the same time, it also provides a non-binary LDPC (NB-LDPC) code set program. Furthermore, the simplified bubble check treasure event count is implemented through the use of first in first out (FIFO), which is based on an elegant design. The structure of the interpreter and the creation of the residential area he built were planned in very high speed integrated circuit (VHSIC) hardware description language (VHDL) and simulated in MODELSIM 6.5. The combined output of the Cyclone II FPGA is combined with the simulation output.

Design and Analysis of NB QC-LDPC Codes Over Small Alphabets

We propose a novel approach to optimization of irregular nonbinary (NB) quasi-cyclic (QC)-LDPC codes over small alphabets. In this approach, first, the base parity-check matrices are constructed by a simulated annealing method, and then these matrices are labeled by the field elements while maximizing the so- called generalized girth of the Tanner graph. In order to analyze the performance of the constructed irregular NB LDPC codes, a new ensemble of irregular NB LDPC codes over the extensions of the binary Galois field is introduced. A finite-length random coding bound on the error probability of the maximum-likelihood (ML) decoding over the binary phase shift keying (BPSK) input AWGN channel for the new code ensemble is derived. The frame error rate (FER) performance of the sum-product belief-propagation (BP) decoding of the constructed NB QC-LDPC block codes is compared to that of both the optimized binary QC-LDPC block codes in the 5G standard and the best known NB QC-LDPC codes as well as to the derived random coding bound on the ML decoding error probability. It is shown that the obtained bound predicts the behavior of BP decoding performance of practical NB QC-LDPC codes more accurately than the BP decoding thresholds do.

Dynamic Multi-Symbol Flipping Decoding of Non-Binary LDPC Codes

A dynamic multi-symbol (DM) flipping scheme is proposed for various symbol flipping decodings of non-binary low-density parity-check (NB-LDPC) codes. This new approach divides the whole decoding process into multiple stages according to the number of iterations and allows a different maximum number of symbols to be flipped in each stage. Numerical analysis reveals that the proposed multi-symbol flipping scheme can yield a higher probability of correct flipping with the dynamic flipping threshold. The proposed DM scheme can be highly parallelized, extensively improving the decoder throughput over existing symbol flipping decoding algorithms based on prediction (SFDP). Numerical results show that the DM scheme can significantly enhance the error correction capability and achieve faster convergence speed with little increase in average computational complexity.

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.