Nominal VDD Research Articles

DC to AC analysis of HC vs. BTI damage in N-EDMOS used in single photon avalanche diode cell

N-channel Extended Drain Metal Oxide Semiconductor (EDMOS) device is analysed through its sensitivity to Hot-Carrier (HC), hot hole (HH) injections and Positive Bias Temperature (PBT) instability degradation using accelerated DC to AC lifetime technique. EDMOS device is optimized for an effective gate-length Leff = 0.25 μm, with a gate-oxide thickness Tox = 5 nm operating at a frequency of 3 MHz at nominal supply voltage VDD = 5 V. The device is used in a mixed structure dedicated to 3D integration of Single Photon Avalanche Diode (SPAD). We show that HC reliability of EDMOS transistor can be obtained using worst-case DC accelerating degradation at high temperature transferred to the real AC waveforms applied to N-channel device placed into the SPAD cell. This allows to deduce the AC device lifetime obtained from DC stressing using a quasi-static approach considering the dominant degradation mechanism at condition of maximum gate-voltage VGSmax. This is explained by the optimized structure in Tox, VDD and lateral isolation where PBT, Off mode and recovery effects have limited impacts during switching operation of the N-EDMOS device used in SPAD circuit environment.

A Timing-Based Split-Path Sensing Circuit for STT-MRAM.

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (VDD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal VDD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time.

Design Techniques for Ultra-Low Voltage Analog Circuits Using CMOS Characteristic Curves: a practical tutorial

The use of ultra-low-voltage (ULV) analog circuits for IoT applications, in which reduced power consumption is a mandatory specification, is becoming more and morean important design approach. Also, in many IoT applications, power is supplied with energy harvested from environmental sources. It is more efficient for the circuit to operate at a voltage level close to the provided by the energy harvester (between 0.3 and 0.6 V). To deal with this when using low-cost technology process nodes - 180-nm, for example, with |VT| ≈0.5V - it is necessary to apply specific design techniques that take advantage of reverse short channel effect, forward bulk bias-ing (FBB) or bulk-driven circuits. The use of low-VT transistors is also a good alternative when they are available inthe target process node. This paper presents a comprehensive scenery about modern CMOS ULV design techniques from the designer’s point of view, including design trade-offs and comments about design decisions. Four step-by-step design examples of ULV circuits are presented: a cross-coupled negative transconductor, a CMOS inverter as an analog amplifier, a pseudo-differential inverter-based amplifier, and a bulk-driven differential amplifier with active load. All designs require the biasing of transistors in moderate and weak inversion regions.The goal is to demonstrate that it is possible to design ULV analog circuits using standard-VT transistors with a supply voltage much lower than the nominal VDD.

A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic

This letter presents an RISC-V microprocessor implemented using a proposed scalable dynamic leakage suppression (SDLS) logic style. Together with a custom adaptive clock generator and voltage scaling controller, the SDLS RISC-V microprocessor realizes a fully integrated modified dynamic voltage and frequency scaling (DVFS) scheme that enables nW-level performance flexibility for battery-less IoT sensing nodes in energy-scarce environments. At the nominal core VDD of 0.6 V, the core can scale its performance from 6 nW at 11-Hz operating frequency to 140 nW at 8.2-kHz operating frequency. Across the supply voltage range, the core is capable of delivering minimum power of 840 pW, maximum frequency of 41.5 kHz, and a minimum energy of 13.4 pJ/cycle.

Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications

Aggressive power supply voltage Vdd scaling is widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical Vdd results to numerous setup timing errors, and hence to an unacceptable output quality. In this paper, we propose computation-skip (CS) scheme to mitigate setup timing errors, for recursive digital signal processors with a fixed cycles per instruction (CPI). A coordinate rotation digital computer (CORDIC) with the proposed CS scheme still functions when scaling beyond the error-free voltage. It enables better-than-worst-case design constraint and achieves 1.82 X energy saving w.r.t. nominal Vdd condition, another 1.49 X energy saving without quality degradation, and another 1.09 X energy saving when sacrificing 8.35 dB output quality.

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Current-mode sense amplifiers (CSA) are commonly used in eNVM, because of their fast read speed at large bitline (BL) loads and small cell read currents. However, conventional CSAs are unable to achieve fast random read access time $(T_{\rm AC})$ , due to significant summed input offsets $(I_{{\rm OS}\hbox{-}{\rm SUM}})$ at read-path. This work proposes a calibration-based asymmetric-voltage-biased CSA (AVB-CSA) to suppress $I_{{\rm OS}\hbox{-}{\rm SUM}}$ and enable high-speed sensing without the need for run-time offset-cancellation operations. This work then fabricated two 90 nm AVB-CSA 1 Mb Flash testchips (with and without BL-length test-modes). The AVB-CSA eFlash macros with 512 rows achieved $T_{\rm AC}$ of 3.9 ns at nominal VDD (1.2 V). The BL-length test-mode experiments confirmed a $1.53\times$ improvement in $T_{\rm AC}$ using AVB-CSA with a BL-length of 2048-rows operating at ${\rm VDD}=0.8$ V.

A 290 mV Sub-V(T) ASIC for Real-Time Atrial Fibrillation Detection.

A real-time detector for episodes of atrial fibrillation is fabricated as an application specific integrated circuit (ASIC). The basis for detection is a set of three parameters for characterizing the RR interval series, i.e., turning point ratio, root mean square of successive differences, and Shannon entropy. The developed hardware architecture targets ultra-low voltage operation, suitable for implantable loop recorders with ultra-low energy requirements. Algorithmic and architectural optimizations are performed to minimize area and energy dissipation, with a total area footprint reduction of 44%. The design is fabricated in 65-nm CMOS low-leakage high-threshold technology. Measurements with aggressively scaled supply voltage (VDD) in the subthreshold (sub-VT) region show energy savings of up to 41 X when operating at 1 kHz with a VDD of 300 mV compared to a nominal VDD of 1.2 V.

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (VWL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal VDD. A specific VWL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a VWL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of VWL with a small impact on read time.

Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects

Microcontrollers play a vital role in embodying intelligence into battery-powered everyday objects to realize the internet of things (IoT). The desirable attributes of such a microcontroller and the like include high energy and area efficiency, and robust error-free operation under dynamic voltage scaling (DVS), workload, process, voltage, and temperature (PVT) variation effects. In this work, a synchronous-logic (S 8051) and a quasi-delay-insensitive asynchronous-logic (A 8051) 8051 microcontroller core are designed and fabricated for full-range DVS from nominal VDD to deep sub-threshold. The performance of the S 8051 and A 8051 are largely comparable at nominal conditions and the entire DVS range, but differs when PVT and workload are varied. At nominal VDD, both the microcontroller cores feature comparable energy and speed, with the electromagnetic interference of the A 8051 ~ 12 dB lower and the area ~ 2 × larger than the S 8051. When DVS is applied, both the microcontroller cores feature comparable energy and speed; the S 8051 requires simultaneous adjustment of clock frequency with VDD. At wide PVT variations, up to ~ 12 × delay margins are required for the S 8051, whereas the A 8051 operates at actual speed. When the workload of both microcontrollers is varied, the A 8051 features lower energy dissipation per workload due to the exploitation of its asynchronous-logic protocols. For IoT applications that incur wide PVT and workload variations, A 8051 is more suitable due to its self-timed nature, whereas when PVT and workload variations are less severe, S 8051 is more suitable due to a smaller IC area.

An ultra‐thin oxide sub‐1 V CMOS bandgap voltage reference

ABSTRACTThis paper presents a sub‐1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling‐induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional (non‐high‐κ/metal gate) ultra‐thin oxide CMOS technologies (tox < 3 nm), where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference (average temperature coefficient, TC_AVG, of 22.5 ppm/°C) overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick‐oxide voltage reference (TC_AVG = 14.0 ppm/°C) as a means of demonstrating that ultra‐thin oxide MOSFETs can achieve performance similar to that of more expensive thick(er) oxide MOSFETs and that they can be used to design the analog component of a mixed‐signal system. The reference was investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. Copyright © 2013 John Wiley & Sons, Ltd.

Sub-threshold synchronizer

Sub-threshold operation has been proven to be very effective to reduce the power consumption of circuits when high performance is not required. Future low power systems on chip are likely to consist of many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold region. Synchronizers are therefore needed to interface between these sub-systems. However, VDD scaling rapidly degrades synchronizers' performance making them unsuitable for sub-threshold operation. For the first time, we analyze the synchronizer performance at ultra low voltages and propose to apply forward body bias to extend the operation of synchronizers to the sub-threshold region and to make them resilient to process variation. We show that applying full-VDD bias significantly increases the transconductance of the bi-stable in synchronizers without adding capacitance to the switching nodes. As a result all the circuit parameters (τ metastability time constant, Td normal propagation delay and Tw metastability window) determining synchronizer performance or mean time between failure (MTBF) can be improved by more than 80% (i.e. by five times) in the sub-threshold region. We also study the impact of process variation on the synchronizer performance in the sub-threshold region and conclude that with full-VDD bias the synchronizer MTBF can be improved from seconds to years for the worst case corner. Finally, we propose an implementation scheme of full-VDD body-biased synchronizer, which is able to work for a wide range of VDDs from sub-threshold region to nominal VDD with nearly zero overhead.

A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing

The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.

DYNAMIC VOLTAGE SCALING CONTINUOUS ADAPTIVE-SIZE CELL DESIGN TECHNIQUE

In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal VDD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage.

A 1-GHz logic circuit family with sense amplifiers

This paper describes a newly developed logic circuit family based on dual-rail bit lines and sense amplifiers that is used extensively in a 1.0-GHz, single-issue, 64-bit PowerPC integer processor, gigahertz unit test site (guTS). The family consists of an incrementor, a count-leading-zero, a rotator, and a read-only memory. Each macro consists of a leaf-cell array, dual-rail bit lines, a row of sense amplifiers, a control block, and peripheral circuits. A common read-out scheme sensing the differential voltage of dual-rail bit lines is used. The hardware was fabricated in a 0.25-/spl mu/m drawn channel length, six-metal-layer (Al) CMOS technology (1.8-V nominal VDD). Wafer testing was performed using a probe card. The macros were tested cycle by cycle by scanning the input data to the read/write address latches and data latches, and scanning the result out from the output receiving latches. Functional testing was performed on guTS macros at frequencies up to 1.0 GHz at 25/spl deg/C with nominal VDD (1.1 GHz for the ROM).

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

This paper describes a 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications. The chip implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-/spl mu/m three-metal CMOS process with 0.35 V thresholds and 0.25 /spl mu/m effective channel lengths. The chip measures 7.8 mm/spl times/6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package.