Nominal Threshold Voltage Research Articles

A 4H-SiC JFET with a monolithically integrated temperature sensor

In this paper, we present a monolithically integrated temperature sensor for a 4H-SiC JFET. This uses a lateral resistor formed by the P+ gate implant. The sensor resistance is dependent on the number of ionized dopants, which increases with temperature. Drift-diffusion simulations considering device self-heating have been carried out, which show the JFET exhibits a breakdown voltage of 1480 V and a nominal threshold voltage (Vth) of −4.3 V. We show that the sensor has a high degree of linearity (R2) of 0.996 between 25–150∘C. Breakdown voltage of the JFET with the integrated sensor is found to reduce as the spacing (S) between the gate junction, the adjacent floating guard ring (FGR) and the sensor junction increases. However, it is found that a large variation in sensor current (ΔIsens) is experienced in the off-state if S is small. An optimum value of S = 0.95 µm was found to maintain 90% of the JFET breakdown voltage, whilst only exhibiting ΔIsens= 3.4%. The impact of contact resistance to the total sensor resistance is ≤1%. In addition, the sensor robustness during switch-off is good, due to the high doping in the P+ layer. The proposed sensor can be integrated into 4H-SiC JFET without any modification of existing process flows, or additional mask layers to provide real-time temperature monitoring with high accuracy.

Optimization of 7 nm Strained Germanium FinFET Design Parameters Using Taguchi Method and Pareto Analysis of Variance

FinFET technology has emerged as an excellent alternative to planar MOSFET for sub-nanometer scaled technology processes in order to achieve high performance and low power. The geometrical parameters of FinFET are particularly sensitive to the devices' figure-of-merits. In this work, the effects of critical geometrical factors of the 7 nm strained germanium FinFET were systematically investigated by studying the resulting I-V characteristics, DIBL, and subthreshold swing. Variation of structure parameters are implemented and optimized using the Taguchi method signal-to-noise ratio with orthogonal arrays of L27 (313) as well as Pareto analysis of variance to obtain the best combinations of parameters for each response performance. The results reveals that the nominal threshold voltage achieved for n-FinFET and p-FinFET are 0.146V and −0.152V respectively. It was observed that design variations were shown to affect n-FinFET more compared to p-FinFET. Drive current can be increased up to approximately 22% for an optimized Ion performance, while leakage can be reduced up to 103 in Ioff optimization. Moreover, it is also observed from the Pareto analysis that the performance of FinFET is mainly affected by the dominant factors of fin length, top fin width, and the interaction of both for n- and p-FinFET by more than 50% for each response.

Annealing, temperature, and bias-induced threshold voltage instabilities in integrated E/D-mode InAlN/GaN MOS HEMTs

Threshold voltage instabilities are examined in self-aligned E/D-mode n++ GaN/InAlN/GaN MOS HEMTs with a gate length of 2 μm and a source-drain spacing of 10 μm integrated in a logic invertor. The E-mode MOS HEMT technology is based on selective dry etching of the cap layer which is combined with Al2O3 grown by atomic-layer deposition at 380 K. In the D-mode MOS HEMT, the gate recessing is skipped. The nominal threshold voltage (VT) of E/D-mode MOS HEMTs was 0.6 and −3.4 V, respectively; the technology invariant maximal drain current was about 0.45 A/mm. Analysis after 580 K/15 min annealing step and at an elevated temperature up to 430 K reveals opposite device behavior depending on the HEMT operational mode. It was found that the annealing step decreases VT of the D-mode HEMT due to a reduced electron injection into the modified oxide. On the other hand, VT of the E-mode HEMT increases with reduced density of surface donors at the oxide/InAlN interface. Operation at the elevated temperature produces reversible changes: increase/decrease in the VT of the respective D-/E-mode HEMTs. Additional bias-induced experiments exhibit complex trapping phenomena in the devices: Coaction of shallow (∼0.1 eV below EC) traps in the GaN buffer and deep levels at the oxide/InAlN interface was identified for the E-mode device, while trapping in the D-mode HEMTs was found to be consistent with a thermo-ionic injection of electrons into bulk oxide traps (∼0.14 eV above EF) and trapping at the oxide/GaN cap interface states.

A Low Voltage Wide-Input-Range Bulk-Input CMOS OTA

The Gm-C technique is extensively used for continuous-time filtering applications because it results in tunable, wideband and compact designs. In this paper, an OTA architecture using a novel bulk-input differential pair without the use of a tail current source is proposed. Good CMRR is still achieved by using the gate terminal to control the total current in the differential pair, via the use of a dummy pair. The OTA also exhibits a wide differential input range and good Gm-tunability. For this design, two standard double-poly double-metal CMOS processes were investigated: a 0.8 ?m process having a nominal threshold voltage of around 0.7 V and a 0.35 ?m process having a nominal threshold voltage of 0.5 V. Simulation results are presented for both designs while test results are presented, for the OTA, implemented using the 0.8 ? m process, used in a second order cochlea low-pass filter.

A 1 V second order Sigma-Delta modulator

A second order switched capacitor sigma-delta modulator operating at a supply voltage of 1 V is presented. This low supply voltage restricts the gate overdrive voltage available for switching transistors. The design relies on the elimination of critical switches by using a modified switched op amp for the integrator and novel switched half-supply and reference voltage generators. The design has been carried out in a fully differential configuration in order to minimize errors arising from charge injection and clock-feedthrough effects. The converter has been implemented using a conventional 0.8 μm double-poly double-metal CMOS process, having a nominal threshold voltage of 0.75 V. Test results, showing more than 9 bits of resolution with an oversampling ratio of 64, are also presented.

Radiation Testing of the CMOS 8085 Microprocessor Family

Preliminary results of radiation testing are reported for parts from the SA3000 family, CMOS versions of the Intel 8085 microprocessor family. Total dose tests of the SA3000 and SA3002 have demonstrated full functionality after 3 × 106 rad (Si). Static power supply currents of the SA3000 measured after reset increased from approximately 5OμA to 500μA at VDD = 1OV while maximum operating frequency decreased from greater than 10 MHz to 4 MHz at VDD = 9V post 3 × 106 rad (Si). Output drive currents decreased 25% post 1 × 106 rad (Si) and 40% post 3 × 106 rad (Si). The nominal threshold voltage shift of discrete transistors measured under worst-case bias (n-channels, ON; p-channels, OFF) shifted -0.5 volts and -2.40 volts post 1 × 106 rad (Si) for n-channel and p-channel MOSFETs, respectively. Total dose tests on the SA3002 are also reported. Transient radiation upset levels of about 1× 109 rad (Si)/sec have been measured for all part types from this family. Latch-up immunity for this technology has been demonstrated up to 1 × 1012 rad (Si)/sec using the SA3001. Electrical bench tests on the SA3000 and SA3001 are discussed which substantiate this result. The technology used for the SA3000 family is a 3μm silicon gate process fabricated in n on n+ epitaxial silicon. Functional test programs for each chip of the family are discussed.

Triggering of Cathode or Emitter Coupled Univibrators Connected into a Chain†

ABSTRACT The possibility of direct triggering of one cathode or emitter coupled univibrator by the differentiated cathode or emitter voltage jump of the other is discussed and analysed, for univibrators connected into a chain. Simple approximate relations are derived for the univibrator optimum trigger pulse nominal threshold voltage and for the maximum permissible deviation from their nominal parameters, which show that this way of triggering is suitable both for transistor and for tube circuits.