Noise-shaping Techniques Research Articles

Improving performance of differential pulse coding modulation based digital mobile fronthaul employing noise shaping.

A differential pulse coding modulation with noise shaping (NS-DPCM) is proposed to achieve better error vector magnitude (EVM) performance in a digital mobile fronthaul. Compared to previous DPCM based digital mobile fronthaul, a feedback loop combined with a finite-impulse-response (FIR) filter is added to the quantizer of DPCM encoder to operate as a quantization noise shaping technique block. The noise shaping technique increases the signal-to-quantization noise ratio by reshaping the spectrum of the quantization noise. Therefore, the noise power is at a lower level in subcarriers of OFDM signal where data is modulated and at a higher level in the subcarriers where no data is modulated. Different from the noise shaping of delta-sigma modulation, the proposed scheme utilizes the existence of unused subcarriers of OFDM signal, thus does not require oversampling at the transmitter and low pass filter at the receiver. In the experiment, the proposed NS-DPCM based mobile fronthaul transmission is demonstrated in a 25-Gb/s PAM-4 intensity modulation-direct detection optical link. Compared to the existing DPCM based mobile fronthaul, significant EVM performance improvement is achieved using the same number of quantization bits.

An iterative LMI algorithm for quantization noise reduction in ΔΣ modulators

In this paper, we design noise shaping filters for quantization noise reduction in ΔΣ modulators. The design problem for the noise shaping infinite impulse response (IIR) filter in the feedback of the ΔΣ modulator is in non-convex form, which is hard to solve in general. We propose an iterative linear matrix inequality (LMI) algorithm to find a near optimal noise shaping IIR filter by solving the non-convex design problem. The least-squares and the hybrid design are two methods, either of which can serve as a starting point for our iterative LMI algorithm to obtain a near optimal solution. We also compare and analyze the performances of some other noise shaping techniques with our proposed algorithm. A design example for a bandpass ΔΣ modulator based radio frequency transmitter is provided which takes into account the non-ideal behavior of the output analog filter.

Synthesis Concepts of Signals With High Spectral Purity for the Use in Impulse Radar Systems

This paper focuses on the synthesis of ultralow-noise signals for the use in a timebase of impulse radar systems. These systems are used in manifold applications and their accuracy is strongly dependent on the spectral purity of the timebase. Current systems use either phase-locked loops (PLLs) or direct digital synthesizers (DDSs). These PLLs comprise an excessive amount of components and recent DDSs still have a low spurious-free dynamic range (SFDR). Therefore, this paper presents two new approaches for the direct synthesis. They are based on frequency dividers with both short division factor sequences and noise-shaping techniques. Ideas for spur avoidance and noise reduction are described to improve the noise behavior in terms of SFDR and phase noise. The presented approaches have been realized in hardware and measurement results are depicted. For the system using frequency dividers with short division factor sequences, the best results are a SFDR better than 117 dB at a signal frequency of 10.7 MHz. The phase noise level is below −140 dBc/Hz at offset frequencies greater than 1 kHz. Regarding the frequency dividers with noise-shaping techniques, no discrete spurious are visible. The phase noise level at offset frequencies greater than 7 kHz is below −150 dBc/Hz. These results are comparable with state-of-the-art PLL concepts and thus confirm the approaches.

A reconfigurable CBP/LP active RC filter with noise-shaping technique for wireless receivers

A reconfigurable complex band-pass (CBP)/low-pass (LP) active-RC filter with a noise-shaping technique for wireless receivers is presented. Its bandwidth is reconfigurable among 500 kHz, 1 MHz and 4 MHz in LP mode and 1 MHz, 2 MHz and 8 MHz in CBP mode with 3 MHz center frequency. The Op-Amps used in the filter are realized in cell arrays in order to obtain scalable power consumption among the different operation modes. Furthermore, the filter can be configured into the 1st order, 2nd order or 3rd order mode, thus achieving a flexible filtering property. The noise-shaping technique is introduced to suppress the flicker noise contribution. The filter has been implemented in 180 nm CMOS and consumes less than 3 mA in the 3rd 8 MHz-bandwidth CBP mode. The spot noise at 100 Hz can be reduced by 14.4 dB at most with the introduced noise-shaping technique.

Reconfigurable hybrid CT/DT delta-sigma modulator with op-amp sharing technique dedicated to multi mode receivers

A novel multi mode low pass hybrid continuous/discrete time delta sigma modulator which is suitable for low power wide band applications is presented in this article. The proposed topology can adapt itself for operating in various signal bandwidths as well as different signal to noise plus distortion ratios (SNDRs). The novelty of the proposed modulator lies in the fact that several techniques have been employed simultaneously that not only can reduce the power consumption, but also it can increase the performance of the modulator. Continuous time integrator is utilized to alleviate the specs for the first stage op-amp. The modulator employs an op-amp sharing technique, which decreases the power consumption dramatically due to elimination of the power hungry adder before the quantizer in the feed forward topology. Another attractive advantage of the proposed modulator is using the noise-shaping enhancement technique which can increase the performance of the modulator without using analog active blocks. The unused block of the modulator can be made inactive to achieve less power dissipation. Behavioral simulations in MATLAB environment show the SNDR of 91/86/73 dB over 0.2/2/20 MHz signal bandwidth.

The Design of a Multi-bit Quantization Sigma-delta Modulator

Sigma-delta ACD has two main parts: analog modulator and digital filter, the performance of modulator determines the performance of sigma-delta ADC, so the design of modulator is very important. The paper introduces the principle of sigma-delta AD modulator with high accuracy and the applied over sampling technique, noise shaping technique and multi-bit quantizer technique. Determining the design scheme of modulator—three bits three orders CIFF(Cascade of integrators, feed forward form) structure, and it makes the behavior level verification for this scheme by Simulink tool in MATLAB. The simulation result shows that multi-bit quantizer modulator can get very high SNR, and based on this result it designs every part of the modulator circuit.

A noise-shaping SAR ADC for energy limited applications in 90 nm CMOS technology

In this paper, an ultra-low-power successive approximation register analog-to-digital converter (ADC) for energy limited applications is presented. The ADC resolution is enhanced by using a noise-shaping technique which does not need any integrator and only uses a finite impulse response (FIR) filter. To provide a first-order noise-shaping, the quantization error is firstly extracted by using the digital-to-analog converter (DAC) dummy capacitor and it is then employed in the error feedback scheme. The proposed structure employs a low-gain and low-swing operational transconductance amplifier (OTA) to realize the FIR filter which operates only at the sampling phase. To minimize the power consumption of the ADC analog part, the OTA is powered off during the conversion phase. The proposed ADC is designed and simulated in a 90 nm CMOS technology using Spectre with a 0.5 V single power supply. The simulated ADC uses a fully-differential 8-bit charge redistribution DAC with an oversampling ratio of 8 and achieves 10.7-bit accuracy. The simulated average power consumption is 4.53 μW and the achieved maximum SNDR and SFDR are 66.1 and 73.1 dB, respectively, resulting in a figure of merit of 27.6 fJ/conversion-step.

Real-Time Perceptual Moving-Horizon Multiple-Description Audio Coding

A novel scheme for perceptual coding of audio for robust and real-time communication is designed and analyzed. As an alternative to PCM, DPCM, and more general noise-shaping converters, we propose to use psychoacoustically optimized noise-shaping quantizers based on the moving-horizon principle. In moving-horizon quantization, a few samples look-ahead is allowed at the encoder, which makes it possible to better shape the quantization noise and thereby reduce the resulting distortion over what is possible with conventional noise-shaping techniques. It is first shown that significant gains over linear PCM can be obtained without introducing a delay and without requiring postprocessing at the decoder, i.e., the encoded samples can be stored as, e.g., 16-bit linear PCM on CD-ROMs, and played out on standards-compliant CD players. We then show that multiple-description coding can be combined with moving-horizon quantization in order to combat possible erasures on the wireless link without introducing additional delays.

A MASH-Controlled Multilevel Power Converter for High-Efficiency RF Transmitters

Envelope tracking (ET) is one of the most promising transmitter architectures proposed to increase the efficiency of modern wireless communication system. An ET transmitter consists of a linear RF power amplifier and a high-efficiency envelope amplifier, which is always a switched-mode power converter. The envelope amplifier provides a varying drain (collector) bias voltage, which tracks the envelope of the RF input signal, for the RF power amplifier. Thus, the RF power amplifier keeps working in high-efficiency region of most of the time. Therefore, the overall efficiency of the transmitter is increased. This paper proposes a multistage noise-shaping-technique-controlled multilevel power converter to perform as the envelope amplifier in an ET transmitter. Experimental results show that the proposed power converter can reproduce any envelope signals with the maximum spectrum component of 300 kHz and give maximum instantaneous power of 20 W. Compared with pulsewidth modulation, the noise-shaping technique can shape the ripple into noise and the noise will be attenuated by the low-pass filter, which results a better performance, while maintaining high efficiency as well.

모바일용 디지털 오디오 스피커를 위한 고효율 드라이버 설계

In this paper, we designed Interpolation FIR(Finite Impulse Response) filter and L-bit SDM(Sigma-Delta Modulator) for small digital audio speaker, which has low power consumption and high output characteristics. In order to achieve high linearity and low distortion performance of the systems, we adopt Type Ⅰ Chevychev FIR filter which has equiripple characteristics in the pass band and proposed high efficient FIR filter structure. SDM is the most efficient modulation technique among the noise shaping techniques. In this paper, we implemented SDM using CIFB(Cascade of Intergrators, Feed-Back) which is generally used in DAC of small digital audio speakers. The proposed SDM structure can achieve high SNR, high-efficiency characteristics and low power consumption in mobile devices. Also considering manufacture of SoC(System on Chip), we performed simulation with Matlab and Verilog HDL to obtain optimal number of operational bits and verified a good experimental results.

Noise-Shaping Gain-Filtering Techniques for Integrated Receivers

In this paper, a new technique for realizing area-efficient, low-noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the passband of the filter. This is illustrated by implementing a programmable noise-shaped post-mixer gain-filtering circuit for a CMOS Mobile-TV tuner. The proposed circuits relax the noise-linearity tradeoff in the receiver chain by providing blocker rejection following the mixer outputs. The filter provides an in-band input referred noise density as low as 7.5 nV/sqrt(Hz). The measured out-of-band IIP3 values are 30 dBV and 31.5 dBV for the 3.8-MHz (DVB-H) and 750-kHz (ISDB-T) modes, respectively. Total current consumption is 5.5 mA from a 1.2-V supply. The gain of the block is programmable to be 0 dB, 8ndB, 14 dB, or 20 dB. The design occupies a die area of 0.28 mm2 in a 65-nm CMOS process covering a frequency band of 700 kHz to 5.2 MHz as a universal mobile-TV integrated baseband gain-filtering solution.

Novel Architecture of Feedforward Second-Order Multibit AD Modulator

This paper proposes novel feedforward architecture of the second-order multibit ΔΣAD modulator with single DAC-feedback topology. The ΔΣAD modulator realizes high resolution by oversampling and noise shaping techniques. However, its SNDR (Signal to Noise and Distortion Ratio) is limited by the dynamic range of the input signal and non-idealities of circuit building blocks, particularly by the harmonic distortion in amplifier circuits. A full feedforward ΔΣAD modulator structure has the signal transfer function of unity under ideal circumstances, which means that the signal swings through the loop filter become smaller compared with a feedbacked ΔΣAD modulator. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced in the feedforward structure because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirements for amplifiers with low supply voltage. However, in conventional feedforward ΔΣAD modulator, an analog adder is needed before quantizer, and especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to extra chip area and power dissipation. In this paper, we propose a novel architecture of a feedforward ΔΣAD modulator which realizes the summation of feedforward signals without additional amplifier. The proposed architecture is functionally equivalent to the conventional one but with smaller chip area and lower power dissipation. We conducted MATLAB and SPICE simulations to validate the proposed architecture and modulator circuits.

Adaptive Noise Cancellation Techniques in Sigma–Delta Analog-to-Digital Converters

Adaptive noise cancellation (ANC) techniques that extract a desired signal from background noise have many applications in different engineering disciplines. In ANC, the corrupted signal is passed through a filter that tends to suppress the noise while leaving the original signal unchanged. This paper demonstrates that the adaptive noise cancellation technique can be embedded in the digital signal postprocessing of a sigma-delta analog-to-digital converter and effectively reduces the quantization noise as well as the thermal noise at the output of the converter. The combination of ANC and the noise-shaping technique enable high-resolution analog-to-digital conversion in wideband applications where noise shaping alone cannot provide enough suppression of quantization noise due to the low oversampling ratio.

A novel noise-shaping DAC for multi-bit sigma-delta modulator

This paper describes a new noise-shaping technique for reducing the noise of the internal digital-analog conversion (DAC) in multi-bit low-pass sigma-delta modulators. The proposed technique works with most existing dynamic element matching (DEM) algorithms to provide noise shaping to the DAC noise. The simulation shows that a 10-dB improvement in the signal-to-noise conversion ratio can be obtained with the proposed noise-shaping with DEM (NSDEM) technique. A dithered DAC employing NSDEM is realized in a 0.35-/spl mu/m CMOS process and the test result shows the first-order high-pass noise shaping to the DAC noise, and validates the proposed concept.

Quadrature /spl Sigma//spl Delta/ modulators with a dynamic element matching scheme

This paper presents a new topology of a multibit quadrature bandpass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor implementations by using the same capacitors to sample the input and the reference of the feedback digital-analog converters (DACs). Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex bandpass case is proposed for the case of multibit feedback DACs.

Noise-shaping techniques applied to switched-capacitor voltage regulators

A delta-sigma control loop for a buck-boost dc-dc converter with fractional gains is presented. This technique reduces the tones caused by the traditional pulse-frequency modulation regulation. The prototype regulator was fabricated in a 0.72-/spl mu/m CMOS process and clocked at 1 MHz. It achieved suppression of tones up to 55 dB in the 0-500-kHz range. The input voltage range was 3-5 V. The output voltage ranged from 1.8 to 4 V for load currents up to 150 mA.

A 14-b direct digital frequency synthesizer with sigma-delta noise shaping

This paper describes a 14-b direct digital frequency synthesizer (DDFS) utilizing a sigma-delta noise shaping technique to reduce spurs arising from phase truncation. A new phase accumulator architecture adopting a second-order sigma-delta modulator is proposed. The sigma-delta noise shaping eliminates periodicity inherent in the phase truncation error. With the proposed phase accumulator, the significant spurs are reduced, and the spectral characteristics of the DDFS are then determined by finite precision of sine-amplitude output. A prototype DDFS IC in 0.25-/spl mu/m CMOS was fabricated on 0.12-mm/sup 2/ die area. The measured spurious-free dynamic range (SFDR) is greater than 110 dB for 16-b phase value and 14-b sine-amplitude output. The fabricated IC consumes 100 mW with a 2.5-V supply, and correctly operates up to 250 MHz.

A Bandpass Mismatch Noise-Shaping Technique for<tex>$Sigma$</tex>–<tex>$Delta $</tex>Modulators

A simple bandpass mismatch noise-shaping technique for /spl Sigma/-/spl Delta/ modulators is presented. This technique uses the data-directed scrambler structure and achieves /spl sim/20 dB improvement in signal-to-noise ratio (SNR) for an oversampling ratio (OSR) of 32. Compared to the technique of bandpass mismatch noise shaping of Lin and Schreier, here, the SNR is improved by /spl sim/ 7dB resulting in a 1-bit improvement in resolution. The selection logic is half the size of the logic in Lin and Schreier and is fully compatible with the low-pass selection logic of Kwan et al.. This compatibility allows implementation of bandpass/low-pass modulator as a single product.

Oversampling and sigma-delta strategies for data conversion

This paper presents an introduction to oversampling techniques and the theory and advantages of sigma-delta (/spl Sigma//spl Delta/) devices for digital-to-analogue conversion (DAC) and analogue-to-digital conversion (ADC) in digital signal processing (DSP) systems. It begins with a discussion of conventional Nyquist-sampling-rate DSP, which is followed by an overview of oversampling and decimation/interpolation techniques to reduce the anti-alias and reconstruction filter specifications. Oversampling strategies to increase the resolution of an N-bit ADC or DAC by reducing the baseband quantisation noise are then presented, and this is followed by a description of the use of /spl Sigma//spl Delta/ noise-shaping techniques and the design of /spl Sigma//spl Delta/ converters. The paper concludes with comments on a few of the application and research areas where /spl Sigma//spl Delta/ devices are having a major impact.

A Nyquist-rate pipelined oversampling A/D converter

Oversampling and noise-shaping techniques, such as /spl Sigma//spl Delta/ modulation, have an inherent tradeoff between accuracy and speed, whereby resolution in amplitude is at the expense of resolution in time. Because their internal circuits must operate over many clock cycles to produce a single result, they have limited data rates and power dissipation is a concern. Much attention has been focused on improving the speed and power of /spl Sigma//spl Delta/ analog-to-digital converters (ADCs) by use of higher-order modulators, multi-bit feedback, and multi-bit architectures with single-bit feedback. However, data rates remain limited to less than a few MHz and are not easily extended. A pipelined oversampling architecture circumvents this speed-resolution tradeoff by performing spatial, rather than temporal, oversampling. It combines the high resolution of /spl Sigma//spl delta/ techniques with the high speed of pipelined converters so that both of these attributes are simultaneously achievable.