NoC Architecture Research Articles

Retraction Note: Tree-based wireless NoC architecture: enhancing scalability and latency

Retraction Note: Tree-based wireless NoC architecture: enhancing scalability and latency

FPGA-based implementation and verification of hybrid security algorithm for NoC architecture

FPGA-based implementation and verification of hybrid security algorithm for NoC architecture

A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks

This comprehensive review explores the advancements in processing-in-memory (PIM) techniques and chiplet-based architectures for deep neural networks (DNNs). It addresses the challenges of monolithic chip architectures and highlights the benefits of chiplet-based designs in terms of scalability and flexibility. This review emphasizes dataflow-awareness, communication optimization, and thermal considerations in PIM-enabled manycore architectures. It discusses tailored dataflow requirements for different machine learning workloads and presents a heterogeneous PIM system for energy-efficient neural network training. Additionally, it explores thermally efficient dataflow-aware monolithic 3D (M3D) NoC architectures for accelerating CNN inferencing. Overall, this review provides valuable insights into the development and evaluation of chiplet and PIM architectures, emphasizing improved performance, energy efficiency, and inference accuracy in deep learning applications.

RETRACTED ARTICLE: Tree-based wireless NoC architecture: enhancing scalability and latency

RETRACTED ARTICLE: Tree-based wireless NoC architecture: enhancing scalability and latency

RLARA: A TSV-Aware Reinforcement Learning Assisted Fault-Tolerant Routing Algorithm for 3D Network-on-Chip

A three-dimensional Network-on-Chip (3D NoC) equips modern multicore processors with good scalability, a small area, and high performance using vertical through-silicon vias (TSV). However, the failure rate of TSV, which is higher than that of horizontal links, causes unpredictable topology variations and requires adaptive routing algorithms to select the available paths dynamically. Most works have aimed at the congestion control for TSV partially 3D NoCs to bypass the TSV reliability issue, while others have focused on the fault tolerance in TSV fully connected 3D NoCs and ignored the performance degradation. In order to adequately improve reliability and performance in TSV fully connected 3D NoC architectures, we propose a TSV-aware Reinforcement Learning Assisted Routing Algorithm (RLARA) for fault-tolerant 3D NoCs. The proposed method can take advantage of both the high throughput of fully connected TSVs and the cost-effective fault tolerance of partially connected TSVs using periodically updated TSV-aware Q table of reinforcement learning. RLARA makes the distributed routing decision with the lowest TSV utilization to avoid the overheating of the TSVs and mitigate the reliability problem. Furthermore, the K-means clustering algorithm is further adopted to compress the routing table of RLARA by exploiting the routing information similarity. To alleviate the inherent deadlock issue of adaptive routing algorithms, the link Q-value from reinforcement learning is combined with the router status based in buffer utilization to predict the congestion and enable RLARA to perform best even under a high traffic load. The experimental results of the ablation study on simulator Garnet 2.0 verify the effectiveness of our proposed RLARA under different fault models, which can perform better than the latest 3D NoC routing algorithms, with up to a 9.04% lower average delay and 8.58% higher successful delivered rate.

Design and Analysis of Four Port Router for Network-On-Chip Applications

System-On-Chip (SoC) is a popular VLSI technology that integrates multiple devices onto a single chip. The Network-On-Chip (NOC) concept, which is a novel paradigm in sophisticated System-On-Chip designs that offers efficient communication throughout the on-chip networks, is used to communicate amongst various devices. The router is the main component in an NoC architecture that is responsible for routing information. Packets are sent through a network by an NoC made up of routers. A routing algorithm divides packets into flow control digits (flits) and determines their paths. The placement of routers is determined by the network topology. In the present work, the main target is to design and analyse the router, which is primarily based on a number of critical factors, including topology, routing algorithm, and packet format. The performance of the suggested router is evaluated and compared to that of the Conventional Wormhole Router (CWHR) with respect to power and slack time (ST). When compared to a traditional wormhole router, the proposed router architecture has 18% less slack. As a result, total power consumption is reduced by 29.3% as compared to traditional wormhole architecture. The architecture is synthesized using Cadence Encounter RTL Compiler using standard 65nm technology.

An efficient asynchronous spatial division multiplexing router for network-on-chip on the hardware platform

The quasi-delay-insensitive (QDI) based asynchronous network-on-chip (ANoC) has several advantages over clock-based synchronous network-on-chips (NoCs). The asynchronous router uses a virtual channel (VC) as a primary flow-control mechanism however, the spatial division multiplexing (SDM) based mechanism performs better over input traffics over VC. This manuscript uses an asynchronous spatial division multiplexing (ASDM) based router for NoC architecture on a field-programmable gate array (FPGA) platform. The ASDM router is configurable to different bandwidths and VCs. The ASDM router mainly contains input-output (I/O) buffers, a switching allocator, and a crossbar unit. The 4-phase 1-of-4 dual-rail protocol is used to construct the I/O buffers. The performance of the ASDM router is analyzed in terms of lower urinary tract symptoms (LUTs) (chip area), delay, latency, and throughput parameters. The work is implemented using Verilog-HDL with Xilinx ISE 14.7 on artix-7 FPGA. The ASDM router achieves % chip area and obtains 0.8 ns of latency with a throughput of 800 Mfps. The proposed router is compared with existing asynchronous approaches with improved latency and throughput metrics.

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

SummaryNetwork on Chip (NoC) is an evolving platform for communications related applications, which are executed on a single silicon chip. There are several routing models in NoC architectures, but the accuracy of these models is limited, and the existing models are degraded because of over and under fitting issues. This research introduces the new deep learning‐based latency aware predictive routing model for on‐chip networks to route packets with better performance and power efficiency. The deep learning model used in this research is a new convolutional residual gated recurrent unit (CRGRU) with queuing theory. Moreover, the source and channel queuing delay is comprised of features to learn spatial and sequential information that improves the overall prediction accuracy. This router is modified by the intrusion of the Router States Monitor unit and the CRGRU hardware engine. The work is executed using the Xilinx platform, and the performance measures like latency and throughput are obtained by varying the network size as , , and and also varying the buffer space and length as , , and , respectively. In addition, the squared correlation coefficient (SCC) and normalized root mean square error (NRMSE) are evaluated and compared with existing learning models to validate the proposed model.

Multiobjective piecewise regressive elitism spotted hyena optimized mapping for 3D NoC architecture design

Multiobjective piecewise regressive elitism spotted hyena optimized mapping for 3D NoC architecture design

Proactive flow control using adaptive beam forming for smart intra-layer data communication in wireless network on chip

Systems-on-chips need numerous predesigned cores to advance. NoC enables Multi-Core SoCs (MC_SoCs). Conventional NoC cores use power and latency on multi-hop wired connections. An effective Wireless Network-on-Chip (WiNoC) architecture can overcome NoC difficulties. On-chip antennas, transceivers, and routers replace multi-hop cable connections with high-bandwidth single-hop wireless networks using WiNoC. Nanotechnology development demands fast data transfer to overcome performance bottlenecks from sharing memory modules and connecting fabrics. This research offers a new Proactive Flow control using Adaptive Beam formation for Smart Intra-layer Data Communication technique(PF_SDC) to optimally use network resources and assure QoS in Wireless Network-on-Chip for next-generation nano-domain technology. Hybrid NoC architecture optimises application admission for data transfer over wired and wireless interconnects. Data traffic is managed by a fuzzy inference-based Intelligent Head Agent (IHA). Queue load predicts router status for the fittest path selection. IHA initiates beams at angles to admit data flow towards the target while utilising the least amount of network power and resources. A simulation model shows that the proposed system may be applied in real-world applications and consumes little power with good throughput.

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

Evaluation of Performance of different routing Algorithm using Noxim

One of the primary methods for examining and testing novel ideas in the Network-on-Chip space is simulation. Noxim simulator enables the analysis of performance for both established wired NoC and new WiNoC architectures. User can modify the size of the network, size of the packet, routing algorithm, various strategy selection and packet injection rate. The simulator evaluates NoCs in terms of various parameters of Network throughput, delay etc. In particular, the user can obtain various assessment metrics such as overall number of received packets/flits, global average throughput, max/min global delay, consumption of total energy. and so on. In comparison to traditional mesh NoC, this paper examines how different routing methods and WiNoC sizes affect network traffic distributions. We analyze PIR, Network throughput parameters of 8*8 mesh networks for various routing algorithms and its impacts are investigated. Simulation of Mesh wireless NOC architecture is validated.

A two-level network-on-chip architecture with multicast support

It is essential for implementing processing systems of edge computing, internet of things (IoT) and wireless multimedia sensor networks (WMSN) to use low-power parallel and distributed architectures with high speed and low power consumption. Most of the artificial intelligence and machine learning applications need to be executed on efficient distributed architectures with multicast support. In this paper, TLAM, a high-performance and low-cost NoC architecture is proposed. TLAM stands for Two-Level network-on-chip Architecture with Multicast support and includes a hybrid path/tree based multicast routing algorithm and a specific two-level mesh topology. The routing algorithm of TLAM is basically working according to the Hamiltonian paths. In the proposed architecture, the topology is partitioned and the two-level links provide an efficient infrastructure for low-cost and low-latency transmission of multicast and broadcast messages between partitions. In TLAM, in addition to multicasting routing algorithm, hardware components for handling multicasting packets are designed in order to achieve performance improvements. The goal is to improve the efficiency and performance, especially latency, while handling both unicast and multicast packets. Experimental evaluations including network-level and router-level analysis with different configurations under various traffic patterns were performed. The evaluations in terms of latency, throughput, area and power consumption, indicate that TLAM provides higher performance, especially for dense multicasting and broadcasting, in comparison with the existing architectures.

Novel NOC Architecture for Designing and Implementing a Low Power Router using FPGA

The NOC architecture assumes critical detail at the same time as making plans correspondence frameworks to machine on chip. A noc engineering is higher-excellent over commonplace shipping, common delivery plan then crossbar interconnection layout intended for a on chip businesses. Improve a nice of provider, Throughput, Congestion and state of being inactive in a NoC, The proposed engineering steadily set up itself concerning device modules, as an instance, package deal based, transfer and statistics parcel size with the aid of various the states of correspondence additionally it is necessity at a run time. Within a network on Chip remained making use of stretched out XY calculation to development execution of correspondence. Proposed configuration work evades a halt then information misfortune in a manner with a assistance of this plan. It is able to accomplish low idleness with excessive statistics thru put. Inside this paper we are getting a beyond strategy and a proceed toward a dynamic reconfigurable transfer in a community on Chip without affecting SoC functionality. Reconfigurable VLSI engineering designed for a switch is a number one answer for a correspondence interface nature of management go adaptability of enterprise, value of chip. 2 The plan is created utilizing verilog HDL language and tried on modelsim to the useful rightness. An layout is created has to conquer a portion of the crucial systems administration issues like prevent and stay bolts. It is moreover executed and attempted on maximum latest Xilinx FPGA for the real execution. This paper affords the particular. Analysis and selection inside the dynamic reconfigurable router in a network on Chip.

A Practical Shared Optical Cache With Hybrid MWSR/R-SWMR NoC for Multicore Processors

Conventional electronic memory hierarchies are intrinsically limited in their ability to overcome the memory wall due to scaling constraints. Optical caches and interconnects can mitigate these constraints, and enable processors to reach performance and energy efficiency unattainable by purely electronic means. However, the promised benefits cannot be realized through a simple replacement process; to reach its full potential, the architecture needs to be holistically redesigned. This article proposes Pho$, an opto-electronic memory hierarchy architecture for multicores. Pho$ replaces conventional core-private electronic caches with a large shared optical L1 built with optical SRAMs. The shared optical cache is supported by Pho$Net, a novel hybrid MWSR/R-SWMR optical NoC that provides low-latency and high-bandwidth communication between the electronic cores and the shared optical L1 at low optical loss. Pho$Net’s unique network arbitration protocol seamlessly co-arbitrates the request and reply sub-networks and facilitates cache requests and replies that optimize for the common case of cache hits. Through Pho$ we solve the problems that render previous designs impractical. Our results show that Pho$ achieves on average 1.41× performance speedup (3.89× max) and 31% lower energy-delay product (90% max) against conventional designs. Moreover, the Pho$Net optical NoC for core-cache communication consumes 70% less power compared to directly applying previously proposed optical NoC architectures.

Design of a Novel Wireless NoC Architecture for Chip Multiprocessor

The Network on chip is a new communication method of System on Chip. It is the main part of multi-core technology. A large number of embedded cores can be combined on a single chip. Due to the multi-hop characteristics of communication, there are some problems in the design of traditional NoC, such as high latency and power consumption. Thus, to handle the communication problem of long-distance transmission of traditional NoC, wireless Networks on Chip (WiNoC) has been proposed. Using WiNoC to design the multi-core System on Chip can significantly reduce the latency and energy consumption of the network. The advantage of using wireless network on chip is to replace the multi-hop path of traditional network on chip with wireless single hop link. However, due to the limited space on the chip and the cost, it is very important to determine the optimal number and correct location of wireless hubs. In this paper, we propose a new method to obtain the optimum configuration of a WiNoC by using the Co-evolutionary Algorithms (CA) and a wireless NoC architecture based on mesh. This work examines the effect of VC and sub-net size on WiNoC performance efficiency and energy under different packet injection rate (PIR) and the number of cores (64, 144 and 256). The simulation experiment of the algorithm proposed in the whole architecture has been implemented on the Noxim platform.

A Minimal Buffer Router with Level Encoded Dual Rail-Based Design of Network-on-Chip Architecture

Asynchronous NOCs are most prominent in present SOC designs, due to their low dynamic power consumption, modularity, heterogeneous nature, and robustness to the process variations. Though asynchronous designs are proved efficient over synchronous counterparts, they have some severe drawbacks when area and speed are considered, due to complex handshake control circuits which increase the static power loss. Quasidelay insensitive (QDI) class of asynchronous NOCs based on 2-phase encoding is proved beneficial for speed and throughput enhancement but with complex design. The work has introduced lightweight minimal buffer router based on LEDR encoding to design a low power, high speed with compact NOC architecture. Then, minimal buffer router with FSM-based arbiter and priority assigner block is designed to enhance the speed, power, and area. This proposed work achieves zero dynamic power consumption with a total power consumption of less than 0.082 W with a router latency of 0.8 ns.

LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures

Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from [Formula: see text] to [Formula: see text] are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is [Formula: see text] to [Formula: see text] with respect to BookSim simulator.

Interconnect support for energy efficient and high bandwidth memory access in CMPs

The increasing number of on-chip cores and a limited number of memory controllers pose a critical problem for off-chip memory bandwidth. In this work, we propose an adaptive hybrid switching strategy with a dual crossbar router to provide low latency paths between cache and memory controllers. The performance is further improved by finding the optimal number and placement of memory controllers using machine learning approach with low overheads. The proposed architecture improves the average bandwidth of the network by 21.03% and reduces the network energy and memory access latency by 12.60% and 20.45%, respectively as compared to the traditional NoC architecture.

Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures

Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures