NMOS Designs Research Articles

Characterisation of HEPAPS4—A family of CMOS active pixel sensors for charged particle detection

Monolithic active pixel sensor technology is a relatively inexpensive and reliable alternative to that of CCDs. Potential scientific applications for these devices include charged particle detection, indirect X-rays and neutron imaging. This paper reports on the characterisation and timing parameters optimisation of three different sensor variants from the HEPAPS4 family. The sensors feature standard three nMOS design but differ in the implementation of the photosensitive element. They have an array of 1024 × 384 pixels of 15 × 15 μ m 2 and 20 μ m epi-layer. Photonic methods are used to measure conversion gain, linearity, signal to noise ratio, dynamic range, pixel to pixel uniformity, dark current and read noise.

High-voltage NMOS design in fully implanted twin-well CMOS

This paper discusses the viability of using last generation CMOS technology to develop a High-Voltage NMOS library for smart power integration.Breakdown voltages of the order of 30 V can be achieved for Gate-Shifted extended drain NMOS devices fabricated in a fully implanted, twin-well, 0.5 μm CMOS core process, aimed for mixed-mode applications, without process modification or any additional mask.The trade-offs of using high overdrive voltages, above nominal supply, to reduce On-resistance is also discussed. According to experiments on prototypes, devices under excessive overdrive voltages over long periods revealed threshold voltage and transconductance variations, due to gate oxide degradation.

Scaling trends for device performance and reliability in channel-engineered n-MOSFETs

Channel-engineered MOSFETs with retrograde doping profiles are expected to provide increased carrier mobility and immunity to short channel effects. However, the physical mechanisms responsible for device performance of retrograde designs in the deep-submicron regime are not fully understood, and general device scaling trends are not well documented. Also, little effort has been devoted to the study of hot-electron-induced device degradation. In this paper, we employ a comprehensive simulation methodology to investigate scaling and device performance trends in channel-engineered n-MOSFETs. The method features an advanced ensemble Monte Carlo device simulator to extract hot-carrier reliability for super-steep-retrograde and more conventional silicon n-MOS designs with effective channel lengths scaled from 800 to 100 nm. With decreasing channel length, our simulations indicate that the retrograde design shows increasingly less total hot-electron injection into the oxide than the conventional design. However, near the 100-nm regime, the retrograde design provides less current drive, loses its advantage of higher carrier mobility, and exhibits much greater sensitivity to hot-electron-induced interface states when compared to the conventional device.

The design and performance of CMOS 256K bit DRAM devices

The design and performance of CMOS 256K bit dynamic random access memory devices with 256K/spl times/1 and 64K/spl times/4 output configurations are presented. An advanced CMOS technology, with device scaling to the HMOS-III level, is used to provide effective solutions to critical device and circuit problems in DRAM design and to offer features not previously implemented in NMOS designs. The cell and die area are 70 /spl mu/m/SUP 2/ and 253 mil /spl square/ (6.3 mm /spl square/), respectively. The typical row access time is less than 100 ns. The p-channel memory array used in this design improves the memory refresh characteristics and reduces the soft error rates. The use of static and clocked CMOS circuits provides lower active power, wide operating margins, microwatt standby power, and high column data bandwidth. The 256K bit devices are designed with two output modes, namely, ripplemode and static column mode, selected by a metal mask option.

Using a hardware simulation engine for custom MOS structured designs

Mixed-level simulation techniques are widely used in VLSI designs for verification and test evaluation. In this paper we indicate how to perform mixed-level simulation on structured MOS designs using the Yorktown Simulation Engine (YSE), a hardware simulator developed at IBM. On the YSE, simulation can be done at the functional, gate, and transistor levels. The design specification used by the YSE is well suited for mixed-level simulation, particularly with regard to interfacing the different levels. We apply our techniques to an nMOS design to show the important features of our approach.

Automated verification of the VLSI design using mock cells

An automated VLSI verification system that has proven effective in production use is described. A unique feature of the system is the use of equivalent mock cells that simplify network reduction and sharply reduce the size of the manipulated data base. Initial application of the system has been with semi-custom NMOS designs, however the process may be applied to any VLSI technology.