High-voltage NMOS design in fully implanted twin-well CMOS

Abstract

This paper discusses the viability of using last generation CMOS technology to develop a High-Voltage NMOS library for smart power integration. Breakdown voltages of the order of 30 V can be achieved for Gate-Shifted extended drain NMOS devices fabricated in a fully implanted, twin-well, 0.5 μm CMOS core process, aimed for mixed-mode applications, without process modification or any additional mask. The trade-offs of using high overdrive voltages, above nominal supply, to reduce On-resistance is also discussed. According to experiments on prototypes, devices under excessive overdrive voltages over long periods revealed threshold voltage and transconductance variations, due to gate oxide degradation.