Nitrided Gate Oxide Research Articles

Body doping dependence of field-effect mobility in both n- and p-channel 4H-SiC metal-oxide-semiconductor field-effect transistors with nitrided gate oxides

Both n- and p-channel SiC MOSFETs, the gate oxides of which were annealed in NO, with various body doping concentrations were fabricated. Despite the large difference in bulk mobility between electrons (1020 cm2 V−1 s−1) and holes (95 cm2 V−1 s−1), the maximum field-effect mobility in heavily-doped (∼5 × 1017 cm−3) MOSFETs was 10.3 cm2 V−1 s−1 for the n-channel and 7.5 cm2 V−1 s−1 for the p-channel devices. The measurements using body bias revealed that the field-effect mobility in both n- and p-channel SiC MOSFETs is dominated by the effective normal field rather than the body doping.

Comparative Study of Hall Effect Mobility in Inversion Layer of 4H-SiC MOSFETs With Nitrided and Phosphorus-Doped Gate Oxides

In this study, the inversion layer mobility characteristics in Si-face 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with nitrided and phosphorus-doped gate oxides were compared using Hall effect measurements. The inversion layer mobility was evaluated by applying a body bias and changing the temperature. The carrier scattering properties were determined for elevated temperatures (i.e., 473 K), at which point the impact of Coulomb scattering decreases and that of phonon scattering increases. The phonon-limited mobility of these MOSFETs was almost the same when plotted as a function of the effective normal electric field in the inversion layer, possibly representing the nature of the thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiC interface. On the basis of this finding, the effect of phonon scattering was separated from the inversion layer mobility. The MOSFETs exhibited a remarkable difference in Coulomb scattering: the MOSFETs with phosphorus-doped gate oxide exhibited a more rapid increase in Coulomb-limited mobility with increasing surface carrier density than did the MOSFETs with nitride gate oxide. This resulted from the effective suppression of Coulomb scattering in the inversion layer, which is one of the reasons why phosphorus-doped gate oxide achieves higher inversion layer mobility than nitrided gate oxide. These results show that the inversion layer mobility of SiC MOSFETs can be modeled using a conventional framework of phonon, Coulomb, and surface roughness scattering. Therefore, the suppression of Coulomb scattering is key to further improving the inversion layer mobility of SiC MOSFETs.

High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

Near-Interface Trap Model for the Low Temperature Conductance Signal in SiC MOS Capacitors With Nitrided Gate Oxides

The low channel-carrier mobility in commercial SiC MOSFETs has been attributed to fast electron traps labeled “NI.” These traps exhibit anomalous behavior compared to other interface trap signals. Furthermore, the electrical parameters extracted from a conventional interface trap analysis of the NI signal are not physically reasonable. To explore the origin of these traps, we fabricated SiC MOS capacitors and measured the conductance across a range of temperatures (between 50 and 300 K). By analyzing the surface electron density at the signal peaks, it is evident that these traps are in fact near-interface traps (NITs)—they are located within the oxide and exchange electrons via a tunneling mechanism. We also developed a model for the conductance generated by NITs and demonstrated a good fit to the experimental data. The knowledge that the NI signal is due to NITs will help in directing future efforts to improve SiC MOSFET performance.

A Comparison of Active Near-Interface Traps in Nitrided and As-Grown Gate Oxides by the Direct Measurement Technique

This paper presents a comparative analysis of the electrically active near-interface traps, energetically located above the bottom of conduction band. Two different samples of N-type SiC MOS capacitors were fabricated with gate oxides grown in (1) dry O2 (as-grown) and (2) dry O2 annealed in nitric oxide (nitride). Measurements performed by the direct measurement method revealed that the traps located further away from the SiO2/SiC interface are removed by nitridation. A spatially localized behaviour of NITs is observed only in the nitrided gate oxide but not in the as-grown gate oxide.

Coulomb-limited mobility in 4H-SiC MOS inversion layer as a function of inversion-carrier average distance from MOS interface

The Coulomb-limited mobility (μCoulomb) of Si-face 4H-SiC MOSFETs with nitrided gate oxide is experimentally evaluated. μCoulomb is experimentally determined using samples with various acceptor concentrations by varying the body bias. It is found that the depletion-charge and surface-carrier densities in the inversion layer can be utilized to well formulate μCoulomb. In addition, μCoulomb is investigated as a function of the inversion-carrier average distance from the MOS interface (ZAV), and it is established that ZAV can universally describe μCoulomb in the inversion layer of Si-face 4H-SiC MOSFETs with nitrided gate oxide.

Hall effect mobility in inversion layer of 4H-SiC MOSFETs with a thermally grown gate oxide

The inversion layer mobility of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with a thermally grown gate oxide was investigated using Hall effect measurements. To clarify the fundamental scattering properties of inversion layer mobility in SiO2/4H-SiC systems, we examined the effects of nitridation treatment after thermal oxidation and the gate oxide thickness on Hall effect mobility (μHall) in the inversion layer of 4H-SiC MOSFETs. The effect of nitridation treatment after thermal oxidation on phonon-limited mobility (μphonon) was investigated by using a p-type well region with an epitaxial layer with extremely low acceptor concentration (NA). It was found that nitridation treatment had little effect on μphonon for gate oxide thicknesses of 5 nm and 50 nm. The carrier transport properties were experimentally evaluated from the viewpoint of the effects of gate oxide thickness and nitridation treatment after thermal oxidation. Here, we used samples with a moderate NA of 1 × 1016 cm−3, which enabled us to distinguish μphonon, Coulomb-limited mobility (μCoulomb) and surface roughness-limited mobility (μSR). It was found that thermally grown SiO2/4H-SiC systems have the common feature that the dominant scattering components in the inversion layer are phonon scattering and Coulomb scattering and not surface roughness scattering at room temperature within the measured effective normal field (Eeff).

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width=82.9nm/8.6nm) have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. The drive current (ION), off current (IOFF), subthreshold swing (SS), drain-induced barrier lowering (DIBL) and transistor gate delay of 30nm gate length (Lg) of FinFETs illustrate the promising device performance. The TCAD simulations demonstrate that both threshold voltage (Vth) and off current can be adjusted appropriately through the full silicidation (FUSI) of CoSi2 gate engineering. Moreover, the drive currents of n- and p-channel FinFETs are able to be further enhanced once applying the raised Source/Drain (S/D) approach technology for reducing the S/D resistance drastically.

Improved Channel Mobility by Oxide Nitridation for N-Channel MOSFET on 3C-SiC(100)/Si

In this work we studied the gate oxidation temperature and nitridation influences on the resultant 3C-SiC MOSFET forward characteristics. Conventional long channel lateral MOSFETs were fabricated on 3C-SiC(100) epilayers grown on Si substrates using five different oxidation process. Both room temperature and high temperature (up to 500K) forward IV performance were characterised, and channel mobility as high as 90cm2/V.s was obtained for devices with nitrided gate oxide, considerable higher than the ones without nitridation process (~70 cm2/V.s).

Analysis of Gate Oxide Nitridation Effect on SiC MOSFETs by Using Hall Measurement and Split C–V Measurement

In this study, 4H–SiC inversion layers were experimentally evaluated by Hall and split C–V measurements, and scattering mechanisms related to gate oxide nitridation were analyzed. Three typical samples with different crystal plane directions and gate oxidation conditions were prepared, and their total trap density and Hall mobility were compared. Based on the temperature dependence of the Hall mobility, we found that scattering mechanisms differed for each sample. The sample C-face oxynitride which had a high nitrogen density at the metal–oxide–semiconductor (MOS) interface, showed a similar temperature dependency to that of ionized impurity scattering. This result suggests that high-density nitrogen acts as donors that supply free carriers and cause ionized impurity scattering, just like in a bulk crystal. In addition, the sample C-face wet has lowest influence of the Coulomb scattering because of the lowest temperature dependence of Hall mobility and the lowest total trap density.

Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method

The threshold-voltage (Vth) shift of 4H-SiC MOSFETs with Ar or N2O post-oxidation annealing (POA) was measured by conventional sweep and non-relaxation methods. Although the Vth shift values of both samples were almost identical when measured by the sweep method, those for the Ar POA samples were larger than those for the N2O POA samples when measured by the non-relaxation method. Thus, we can say that investigating the exact Vth shifts using only the conventional sweep method is difficult. The temperature-dependent analysis of the Vth shifts measured by both methods revealed that the N2O POA decreases charge trapping in the near-interface region of the SiO2.

Two-component model for long-term prediction of threshold voltage shifts in SiC MOSFETs under negative bias stress

The negative bias temperature instability in SiC MOSFETs was investigated. Considering the time, temperature, and bias dependences of the threshold-voltage (Vth) shift, we propose a two-component model for long-term prediction. On the basis of fitting results, we discuss the origins of these components. The first component, which dominates short-term instability, was found to show reverse temperature and weak bias dependences. Such trends are consistent with the carrier exchange of pre-existing slow oxide traps, which are O vacancies. After subtracting the first component, the second component was found to show power-law time dependence, similar to that observed in Si devices. The forward temperature and strong bias dependences of the second component indicate the activation of additional traps. The activation energy of 0.1 eV is consistent with that of a Si device using nitrided gate oxide. Therefore, the origin of the long-term Vth shift of SiC-MOSFETs was suggested to be a nitrogen-related site. Control of the amount of nitrogen is expected to be important for the long-term threshold stability of SiC-MOSFETs.

Threshold Voltage Instability in 4H-SiC MOSFETs With Phosphorus-Doped and Nitrided Gate Oxides

Threshold voltage instability was investigated for 4H-SiC MOSFETs with phosphorus-doped (POCl3-annealed) and nitrided (NO-annealed) gate oxides. Threshold voltage shift observed in the bidirectional drain current–gate voltage characteristics was evaluated using various gate voltage sweeps at room and elevated temperatures up to 200 °C. The threshold voltage shift was also studied after applying positive and negative bias-temperature stress. Two types of MOSFETs showed different instability characteristics, depending on gate biases and temperatures. These features were found to originate from the difference in trap density and trap location at/near the oxide/SiC interface and in the oxide. It is apparent that the oxide traps in phosphorus-doped oxides and near-interface traps in nitrided oxides are the main origin of the threshold voltage instability via capture and emission (in the case of oxide traps, only capture) of both electrons and holes.

0.13㎛ 기술의 shrink에 따른 DC Parameter 매칭에 관한 연구

본 논문은 기존의 poly length만의 축소와 달리 입, 출력 소자를 포함한 core 디바이스의 <TEX>$0.13{\mu}m$</TEX> 디자인을 10% 축소하는 것으로 여러 채널 길이에 따른 body effect와 doping profile simulation을 해석하였다. 축소 전의 DC 파라미터 매칭을 위하여 게이트 산화막의 decoupled plasma nitridation 처리와 LDD(Lightly Doped Drain) 이온주입 전 TEOS(Tetraethylortho silicate) 산화막 <TEX>$100{\AA}$</TEX> 그리고 LDD 이온주입을 22o tilt-angle(45o twist-angle)로 최적화하였고 그 결과 축소 전의 5%의 범위에서 매칭됨을 확인하였다. This paper relates 10% shrink from <TEX>$0.13{\mu}m$</TEX> design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide <TEX>$100{\AA}$</TEX> before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.

Nitridation Effects of Gate Oxide on Channel Properties of SiC Trench MOSFETs

We have studied gate oxide processes for SiC trench MOSFETs. It is demonstrated that nitridation of gate oxide is effective to suppress the variation of channel mobility depending on channel plane orientation and substrate off-angles. In addition, improved channel mobility has been obtained by the combined process of NH3 and N2O POA.

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

In this paper, the dependence of negative bias temperature instability (NBTI) and low-frequency noise characteristics on the various nitrided gate oxides is reported. The threshold voltage shift (ΔVT) under NBTI stress for thermally nitrided oxide (TNO) was greater than that of plasma nitrided oxide (PNO), whereas the slopes of ΔVT versus stress time for PNO were similar to those for TNO. The flicker noise (1/f noise) characteristic of PNO was better than that of TNO by about 1 order of magnitude, although the 1/f noise of PNO showed almost the same dependence on the frequency as that of TNO. The carrier number fluctuation model due to the trapping and detrapping of electrons in oxide traps was found to be a dominant mechanism of flicker noise. The probability of the generation of drain current random telegraph signal (ID–RTS) noise shows similar values (70–78%) for all nitrided oxides, which shows that the generation of RTS noise is not greatly affected by the nitridation method or nitrogen concentration.

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

Reliability of Nitrided Gate Oxides for N- and P-Type 4H-SiC(0001) Metal–Oxide–Semiconductor Devices

In this paper, we have investigated reliability of n- and p-type 4H-SiC(0001) metal–oxide–semiconductor (MOS) devices with N2O-grown oxides and deposited oxides annealed in N2O. From the results of time-dependent dielectric breakdown (TDDB) tests, it is revealed that the N2O-grown oxides have relatively-high reliability (4–30 C cm-2 for n- and p-MOS structures). In addition, the deposited SiO2 on n- and p-SiC exhibited a high charge-to-breakdown of 70.0 and 54.9 C cm-2, respectively. The n/p-MOS structures with the deposited SiO2 maintained a high charge-to-breakdown of 19.9/15.1 C cm-2 even at 200 °C. The deposited SiO2 annealed in N2O has promise as the gate insulator for n- and p-channel 4H-SiC(0001) MOS devices because of its high charge-to-breakdown and good interface properties.

Reliability of Nitrided Gate Oxides for N- and P-Type 4H-SiC(0001) Metal–Oxide–Semiconductor Devices

Reliability of Nitrided Gate Oxides for N- and P-Type 4H-SiC(0001) Metal–Oxide–Semiconductor Devices