NiSi Layer Research Articles

A comparative study of C, N and Xe pre-amorphization implantation processes for improving the thermal stability of NiSi films

In this paper, a comparative study of C-, N- and Xe-based pre-amorphization implantation (PAI) processes is proposed. The impact of the use of such processes on the agglomeration resistance and physical properties of the final Ni(Pt)Si layer, as well as the formation mechanisms via solid-state reactions and electrical performances via the transfer length measurement (TLM) method, is evaluated. It is shown that although all species are able to increase the agglomeration temperature of Ni(Pt)Si layers (up to more than 100 °C), the underlying mechanisms are different. For C- and N-based PAI processes a strong chemical effect is observed, while for Xe-based processes the amorphization depth plays an important role. Consequently, the beneficial effect of stabilizing Ni(Pt)Si layers at high temperatures using C- and N-based PAI processes has to be balanced with an increased layer resistivity (up to 30%) combined with a strong deterioration of the associated specific contact resistivity (which is multiplied by almost a factor 10). In this sense, Xe-based PAI processes seem to be a better option as they could allow to combine both requirements.

C54-TiSi2 formation using nanosecond laser annealing of A-Si/Ti/A-Si stacks

Low resistive Ti-based contacts are required to reach the targeted performances of 3D imaging devices. To fulfill this request, the C54-TiSi2 phase appears to be the most efficient. However, in view of monolithic integration, the temperature needed to form C54-TiSi2 must be drastically reduced by at least 100 °C in order to avoid damage in other parts of the device. Indeed, as these 3D imaging devices require the co-integration of Ti and Ni based silicides, it is crucial to develop a thermal treatment which allows to form the C54-TiSi2 phase without agglomerating the NiSi layer (i.e. at temperatures lower than 600 °C). In this work, a three-layer stack made of a Ti layer in between two amorphous Si thin films deposited on (100) Si substrate has been studied. Nanosecond laser annealing (NLA) followed by rapid thermal annealing (RTA) from 500 to 800 °C were performed on those stacks. Sheet resistance and X-Ray Diffraction measurements showed that the C54-TiSi2 phase could be formed with a RTA treatment at a temperature as low as 600 °C in this case. In line with some previous work, this was due to another phase sequence involving the C40-TiSi2 during the laser annealing. The most favorable microstructure to form C54-TiSi2 by a subsequent RTA treatment seemed to be a matrix made of amorphous titanium silicide containing grains of the C40-TiSi2 template phase. This hypothetical microstructure was formed by laser annealing at a lower energy density when layers of amorphous Si were used.

Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

AbstractA pulsed laser annealing method is utilized to directly synthesize nickel silicide (NiSi) as a contact material to improve the contact of electric devices. Three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), are used for the NiSi synthesis during the pulsed laser annealing process. A NiSi phase with low sheet resistance is formed by an ultraviolet laser annealing (ULA) process without damaging the polyimide (PI) substrate. With the integration of the ULA process‐induced NiSi into p‐nnel MOSFET (PMOS) and n‐channel MOSFET (NMOS) devices, the on/off ratio improves significantly, and the field‐effect mobility increases by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ. In addition to the PMOS and NMOS, the gains of the CMOS inverter at different Vdd values are improved by at least 30%. Moreover, the static noise margin of 6T‐SRAM is elevated from 0.82 to 1 V at Vdd = 4 V. The ability of the ULA process to synthesize a high‐quality NiSi layer on a flexible substrate is demonstrated. The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices.

Narrow Line Width Ni–Cu–Sn Front Contact Metallization Patterns for Low‐Cost High‐Efficiency Crystalline Silicon Solar Cells using Nano‐Imprint Lithography

An in‐house‐developed nanoimprint lithography system is designed and developed to demonstrate a commercially viable method for creating Ni–Cu–Sn‐based narrow linewidth finger patterns capable of effectively reducing shadow loss in the front contact metallization on industrial silicon solar cells. Finite element analysis simulation studies estimate that an optimal force of 138 MPa is required to generate damage‐free patterns during nanoimprinting process. The poly (methyl methacrylate) residual layer is removed using reactive ion etching, which enhances the adhesion strength of Ni–Cu–Sn metallization. A low ohmic contact layer at the Si/Ni interface develops after sintering at 420 °C and formation of NiSi layer is confirmed through X‐ray photoelectron spectroscopy analysis as a function of Ar+ ion etching time. An average cell efficiency of 18.10% is achieved for silicon solar cells with micropatterned Ni/Cu/Sn‐based narrow linewidth front contact grid design, which can exhibit ≈1% enhancement in cell efficiency compared to commercial Ag screen‐printed solar cells. The Ni/Cu/Sn‐based front contact metallization can improve the cell performance by ≈6% compared to the commercial Ag screen‐printed metallization by reducing shadow loss and thereby indicating its suitability toward deploying for cost‐effective industrial solar cell manufacturing.

(Invited, Digital Presentation) Approach to Neuromorphic Computing with Ferroelectric Schottky Barrier FETs

Neuromorphic computing inspired by neural network systems of the human brain enables energy efficient computing as a solution of the von Neumann bottleneck. A neural network consists of thousands or even millions of neurons which communicate with each other through connected synapses. Synapses can memorize and process the information simultaneously. The plasticity of a synapse to strengthen or weaken its activity over time make it be capable of learning and computing. Thus, artificial synapses which can emulate functionalities and the plasticity of bio-synapses form the backbone of a neuromorphic computing system.Non-volatile memories with two-terminals, like resistive random-access memory (ReRAM), phase change memory (PCM), are attractive candidates for artificial synapses. However, signal processing and learning cannot be performed simultaneously in these two-terminal synapses. FeFET, similar to a MOSFET structure using CMOS compatible HfO2 based ferroelectrics as gate oxide forms three-terminal synapses offering high endurance, good performance and high energy efficiency. In contrast to two-terminal devices, three terminal FeFET based synapses can perform processing and learning at the same time. In order to maintain the ferroelectric properties of an HfO2 based ferroelectric film, high temperature annealing should be avoided after the ferroelectric layer deposition. In this paper, we present ferroelectric NiSi2 source/drain Schottky barrier (SB) MOSFET (FE-SBFET) structure (Fig.1a), which requires neither ion implantation nor thermal activation of source/drain contacts at high temperatures.FE-SBFETs were fabricated on SOI substrates with a boron-doped (1016 B/cm-3), 55 nm thick top Si layer and a 145 nm thick buried oxide (BOX) layer. Very thin (9 nm) single crystalline NiSi2 layers which offer superior properties of uniform and stable SB contacts on Si are used at source/drain regions. A gate stack consisting of 10 nm thick Hf0.5Zr0.5O2 (HZO) layer and a 40 nm thick TiN layer are deposited by ALD and sputtering, respectively. A rapid thermal annealing at 500 °C is performed to crystallize the HZO into a ferroelectric phase before the gate patterning. The fabricated device has a channel length of 10 µm and a gate width of 10 µm. The overlap between the top gate and NiSi2 is 6 µm along the channel and 10 µm wide on each side. The ferroelectric polarization modulates both the SB at the source/drain contacts as well as the potential in the channel, thus changing the carrier injection through the SB. The Id-Vg transfer characteristics of a p-type FE-SBFET shows a clockwise hysteresis which is caused by the ferroelectric polarization switch.The excitatory post-synaptic current (EPSC), one of the typical short-term synaptic plasticity features for biologic synapses, is characterized by measuring the transient drain currents for a voltage pulse on the gate of a FE-SBFET (Fig.1b). The amplitude of the pulse VAM changes from -0.2 to -1.2 V with a fixed pulse width tpw=1 μs. We found that the EPSC peak value increases linearly with VAM. It shows a very low energy/spike consumption of 2fJ/spike at VAM=-0.2 V, demonstrating a very high energy efficiency. From the EPSC measurements with repeated gate voltage pulses paired-pulse facilitation/depression (PPF/PPD) are characterized showing an exponential decay, similar to biological synapses.The long-term synaptic plasticity of FE-SBFET synapses is characterized by a series repeated identical or non-identical pulses. The later can improve the long-term potentiation/depression (LTP/LTD) symmetry and linearity. The measurements show a large Gmax/Gmin ratio, very high endurance and small cycle-to-cycle (CTC) variation (1.06%) due to the perfect contact of NiSi2 (Fig.1c). The biological neuron-like spike-timing-dependent plasticity (STDP) is characterized for the FE-SBFET synapse. The results show an asymmetric anti-Hebbian STDP, which is one of the biological STDP functionalities (Fig.1d).In conclusion, the fabricated FE-SBFET synapse exhibits multiple synaptic functions with high endurance and small variations. The ultra-low energy/spike consumption indicates a high potential for low power neuromorphic computing applications. Acknowledgement: This work was supported by the Federal Ministry of Education and Research (BMBF, Germany) in the project NEUROTEC (16ME0398K). Figure 1

The straightforward fabrication of thin silicide layers at low temperatures by employing the molecular-incident reaction effect

Because of the ease of formation, and good lattice match with Si, metal silicides often form high-quality epitaxial layers and have established themselves over the years as important technological materials with industrial applications. For the fabrication of silicon-based devices, the contact between metal electrodes and Si is a key issue. The properties of thin films on silicon substrates are strongly dependent on their microstructure and local chemistry. However, a concrete understanding of the influence of a silver layer on different transition metal/silicon interfaces is not currently available. We propose, for the first time, a new model called molecular-incident reaction effect (MoIRE) model that successfully explains the different chemical reactions for Co/Si and Ni/Si interfaces by the introduction of a 3×3R30o-Ag layer. The interaction transfer of silicon atoms forms a Co silicide for Co/3×3R30o-Ag/Si(111) with a thickness of a few nanometers, thus greatly reducing the temperature needed for the formation of a layered CoSi2 silicide compared to that for typical CoSi2 silicide formation at a Co/Si interface. Based on the MoIRE mechanism, the introduction of the 3×3R30o-Ag layer as an intermediate layer permits the silicidation temperature needed to produce a NiSi layer to be reduced to 400 K from typically above 600 K. This approach is advantageous for the formation of a silicide at the Ni/Si interface at low temperature. Based on the MoIRE model for silicide formation at Ni/3×3R30o-Ag/Si(111), we propose a technique for the synthesis Ni silicide layers at lower temperatures with simpler fabrication steps due to the difference in the properties between Co and Ni. This mechanism of low-temperature fabrication includes the formation of (1) a 3×3R30o-Ag and (2) a NiSi layer. The findings presented herein will be useful for more efficiently forming salicides in integrated circuit fabrication, as well as for developing superconducting circuits and quantum bits for quantum computing.

Metal Sheet of Atomic Thickness Embedded in Silicon.

The controlled confinement of the metallic delta-layer to a single atomic plane has so far remained an unsolved problem. In the present study, the delta-type structure with atomic sheet of NiSi2 silicide embedded into a crystalline Si matrix has been fabricated using room-temperature overgrowth of a Si film onto the Tl/NiSi2/Si(111) atomic sandwich in ultrahigh vacuum. Tl atoms segregate at the growing Si film surface, and the 1.5-3.0 nm thick epitaxially crystalline Si layer forms atop the NiSi2 sheet. Confinement of the NiSi2 layer to a single atomic plane has been directly confirmed by transmission electron microscopy. The NiSi2 delta-layer demonstrates a p-type conductivity associated with the electronic transport through the two hole-like and one electron-like interface-state bands. The basic structural and electronic properties of the NiSi2 delta-layer remain after keeping the sample in air for one year.

(Invited) Nickel and Nickel-Platinum Silicide for BiCMOS Devices

Recently, the world’s fastest SiGe-HBT was presented by IHP researchers [1], which applies low ohmic nickel silicide (NiSi). Among other measures, this feature contributed to speed improvements. On the other hand, the integration of low-ohmic NiSi creates the risk for NiSi defects which could result in increased MOSFET leakage currents. The goal of this contribution is to find out from several two-step silicidations of Ni or NiPt layers a suitable process for a BiCMOS technology which enables low silicide RS for high cutoff frequencies of bipolar and MOS transistors without degradation of leakage currents. In result, a 300°C/450°C silicidation is proposed providing RS values of 3 to 4 Ω for both NiSi and NiPtSi. However, only the NiPtSi shows acceptable low leakage currents compared to NiSi. Therefore, NiPt extends the silicide process window for HBTs and MOSFETs.The phase transitions of Ni and NiPt silicides as a function of temperature are shown in Fig. 1, where the temperature range of the targeted NiSi phase is enlarged for NiPt compared to Ni. The investigated two-step NiSi formations are listed in Table 1. The NiPt layers were deposited in an Applied Materials laboratory. First, Ni2Si was formed by furnace anneal, low pressure anneals, or by a NiPt sputtering at 400°C. The Ni rich silicide was converted into NiSi by a second anneal at 450°C.The final Ni(Pt)Si sheet resistance (RS Ni(Pt)Si:1.+2.Ann) was tunable from 1.5 Ω to 10.5 Ω by the temperature and time of the first anneal (Fig. 2). At 300°C, the RS saturates at 3.3 Ω for 20 nm Ni and 1.6 Ω for 40 nm Ni, respectively. This indicates full Ni consumption. The furnace anneals at 200°C and 230°C do not show any RS saturation since Ni is consumed only partially. An RS increase for NiSi and NiPtSi on PSD (p source-drain) compared to NiSi on substrate is observed.One figure of merit of SiGe-HBTs is the maximum oscillation frequency fmax, which depends by the following equation fmax=sqrt(fT/(8πrBcBC)) on the transit frequency fT, the base resistance rB, and the collector-base capacitance cBC. A silicide resistance variation could mainly influence rB. In Fig. 3a, the sheet resistance of the silicided base polysilicon (RS BasePolySilicide) together with fmax of two HBT layouts are plotted for several silicide formations. It exists a correlation between fmax and RS BasePolySilicide, which is shown in Fig. 3b. In general, fmax could be enlarged by a silicide resistance reduction for special HBT layouts.For these low-ohmic and thick Ni(Pt)Si layers, special attention has to be paid to the MOSFET leakage currents, which can be enlarged by lateral silicide pipes towards the conducting channel or by defects along the SD – STI (shallow trench isolation) interface [2]. Another leakage current source are silicide spikes shortening in a perpendicular direction the SD and the well. Three types of P+Nwell and N+Pwell diodes are suitable to determine and distinguish these silicide based yield killers: area diodes to detect spikes, STI separated island diodes to recognize SD-STI defects, and diodes with long poly-gates on SD-well areas to determine pipes at gate edges. In result, the area and island diodes showed no leakage current increase for the studied silicidations, i.e. defects along the SD-STI edge and spikes are not critical here. The leakage currents of gate-edged diodes on N+Pwell and P+Nwell are presented in Fig.4. Both diode types show low leakage currents for the 200°C and 230°C anneals, because the low lateral silicidation at these temperatures reduces the probability for piping. At 300° the N+Pwell leakage current increases slightly up to 2x10-9A, but significantly up to 1x10-7A for the P+Nwell diode. This is a clear indication for pipes at the gate edges [3]. In contrast, almost no enhanced leakage current was observed for the NiPt silicidations with 200° to 300°C anneals. The pipe suppression of the NiPt silicide system might be caused by the Pt agglomeration at the silicide-SD interface [4]. The limits of the NiPt pipe suppression are shown for N+Pwell diodes silicidated with a NiPt deposition at 400°C. Leakage currents of 1x10-8A could indicate NMOS-typical pipes, as described by Yamaguchi [5].In summary, silicide layers with low RS values of 3Ω to 4Ω were formed by two-step annealing of Ni and NiPt at 300°C and 450°C. These silicides support high fmax values of SiGe HBTs. However, only the NiPt silicide process provided acceptable low leakage currents of MOSFET test structures indicating an extended process capability of NiPtSi compared to NiSi. Figure 1

(Invited) Nickel and Nickel-Platinum Silicide for BiCMOS Devices

The world’s fastest SiGe HBT was presented by Heinemann et al. at IEDM 2016, which was achieved among other measures by NiSi application. The BiCMOS integration of such HBTs requires a careful NiSi adjustment with respect to MOSFET leakage currents. The goal of this paper is to find out a NiSi or NiPtSi process, which results in low RS to increase fmax without degradation of MOSFET leakage currents. An fmax rise is demonstrated by a reduction of NiSi or NiPtSi RS to 4 Ω. A further RS lowering to 1.6 Ω with a corresponding fmax increase was achieved by NiSi layers formed by two-step 300/450°C anneals, which generate elevated MOSFET leakage currents. They can be inhibited for NiSi formed by 200/450°C anneals at the expense of elevated RS. NiPtSi significantly suppresses silicide pipes to the MOSFET channel even for 300/450°C anneals and is a promising choice for upcoming BiCMOS technologies.

Fabrication and characterization of a single monolayer NiSi2 sandwiched between a Tl capping layer and a Si(1 1 1) substrate

Single monolayers of various materials (e.g. graphene, silicine, bismuthene, plumbene, etc) have recently become fascinating and promising objects in modern condensed-matter physics and nanotechnology. However, growing a monolayer of non-layered material is still challenging. In the present study, single monolayer NiSi2 on Si(1 1 1) was grown for the first time, using Tl monolayer as a surfactant and stabilizer. The structural and electronic properties of the Tl/NiSi2/Si(1 1 1) system were characterized using a set of experimental techniques, including low-energy electron diffraction, scanning tunneling microscopy, angle-resolved photoelectron spectroscopy, in situ four-probe transport measurements, and also first-principles density-functional-theory calculations. Nickel atoms were found to reside in the interstitial sites inside the first silicon bilayer of bulk-like-terminated Tl/Si(1 1 1)1 1 surface, with the thallium initial positions remaining almost unchanged. The electronic band structure of the system is clearly metallic, and contains electron and hole pockets related to the Tl and NiSi2 layers, respectively. The surface-state bands are spin-split due to the presence of a Tl layer with a strong spin–orbit coupling. Our transport measurements proved that the Tl/NiSi2/Si(1 1 1) system demonstrates a metallic-type conductivity down to 2.0 K, which is the lowest temperature accessed in the experiment.

Microstructural Analysis of Ti/Ni Bilayer Ohmic Contacts on 4H-SiC Layers

The micro-structural analysis of Ti/Ni bilayer as Ohmic contacts to n-type 4H-SiC is reported. There was no carbon segregation at the interface between the NiSi layer and the 4H-SiC layer for Ti/Ni contacts, unlike pure Ni contacts. The diffraction pattern image shows the presence of the cubic NiSi film which grows on the SiC surface. The film interface with the SiC was uniform and more planar. An optimized contact in terms of contact morphology was achieved using a bilayer contact Ti/Ni (20/100nm) annealed at 1100 °C for 5 minutes in vacuum.

Enhancing silicide formation in Ni/Si(111) by Ag-Si particles at the interface

Compound formation at a metal/semiconductor interface plays crucial roles in the properties of many material systems. Applications of Ni silicides span numerous areas and have the potential to be used as new functionalities. However, the magnetic properties of ultrathin Ni layers on silicon surfaces and related chemical compositions at the interface are not fully understood and the influence of Ag additives on the reactivity of Ni/Si(111) remain unclear. We report herein on the fact that the dominant species produced at the interface is NiSi, which is produced by the spontaneous formation of strong bonds between Ni and Si atoms. Assuming that a Ni layer is formed over a NiSi layer with the total coverage as a constraint, we established a chemical shift-related concentration model that, in effect, represents a practical method for determining the amount of ultrathin Ni silicides that are produced at the buried interface. The formation of Ag-Si particles provide a viable strategy for enhancing silicide formation via a specific interaction transfer mechanism, even at room temperature. The mechanism is related to differences in the enthalpies of formation ΔHAg-Si, ΔHNi-Ag, and ΔHNi-Si, for these phases and provides insights into strategies for producing ultrathin silicides at a buried interface.

Transparent nanoporous P-type NiO films grown directly on non-native substrates by anodization

While electrochemical anodization has been used to form a number of nanostructured n-type semiconducting metal oxides for optoelectronic device applications, there exists a dearth of p-type metal oxide films that are solution processable. Herein, we formed p-type semiconducting NiO films by vacuum depositing Ni thin films on non-native substrates (transparent conductive oxide (TCO)-coated glass substrates and silicon wafers) using magnetron sputtering, and subsequently anodizing and annealing the Ni films. The Ni films were subjected to electrochemical anodization in diethylene glycol based organic electrolytes and subsequently annealed at 600 °C to form nanoporous NiO films with a pore size of ~ 20 nm. Runaway etching is a key issue in Ni anodization which was mitigated through the use of ice bath cooling and galvanostatic anodization. The choice of substrate is found to be critical to the resulting morphology owing to the differing surface roughness. Crystalline NiO is found to have formed from Ni(OH)2 and NiOOH during annealing, and an additional NiSi layer is noted for NiO films on Si wafers. The bandgap of the NiO was estimated to be 3.5 eV. Electrochemical impedance spectroscopy and Mott–Schottky analysis confirmed p-type semiconducting behaviour, and enabled measurement of an acceptor density (NA) of 2.85 × 1018 cm−3 and a flatband potential (VFB) of 0.687 V versus Ag/AgCl.

Efficient and Stable Silicon Microwire Photocathodes with a Nickel Silicide Interlayer for Operation in Strongly Alkaline Solutions.

Most photoanodes commonly applied in solar fuel research (e.g., of Fe2O3, BiVO4, TiO2, or WO3) are only active and stable in alkaline electrolytes. Silicon (Si)-based photocathodes on the other hand are mainly studied under acidic conditions due to their instability in alkaline electrolytes. Here, we show that the in-diffusion of nickel into a 3D Si structure, upon thermal annealing, yields a thin (sub-100 nm), defect-free nickel silicide (NiSi) layer. This has allowed us to design and fabricate a Si microwire photocathode with a NiSi interlayer between the catalyst and the Si microwires. Upon electrodeposition of the catalyst (here, nickel molybdenum) on top of the NiSi layer, an efficient, Si-based photocathode was obtained that is stable in strongly alkaline solutions (1 M KOH). The best-performing, all-earth-abundant microwire array devices exhibited, under AM 1.5G simulated solar illumination, an ideal regenerative cell efficiency of 10.1%.

Redistribution of phosphorus during Ni0.9Pt0.1-based silicide formation on phosphorus implanted Si substrates

Phosphorus diffusion and its distribution during the solid-state reactions between Ni0.9Pt0.1 and implanted Si substrates are studied. Silicidation is achieved through a first rapid thermal annealing followed by a selective etching and a direct surface annealing. The redistribution of phosphorus in silicide layers is investigated after the first annealing for different temperatures and after the second annealing. Phosphorus concentration profiles obtained thanks to time of flight secondary ion mass spectrometry and atom probe tomography characterizations for partial and total reactions of the deposited 7 nm thick Ni0.9Pt0.1 film are presented. Phosphorus segregation is observed at the Ni0.9Pt0.1 surface and at Ni2Si interfaces during Ni2Si formation and at the NiSi surface and the NiSi/Si interface after NiSi formation. The phosphorus is evidenced in low concentrations in the Ni2Si and NiSi layers. Once NiSi is formed, a bump in the phosphorus concentration is highlighted in the NiSi layer before the NiSi/Si interface. Based on these profiles, a model for the phosphorus redistribution is proposed to match this bump to the former Ni2Si/Si interface. It also aims to bind the phosphorus segregation and its low concentration in different silicides to a low solubility of phosphorus in Ni2Si and in NiSi and a fast diffusion of phosphorus at their grain boundaries. This model is also substantiated by a simulation using a finite difference method in one dimension.

Low-Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach.

The race for performance of integrated circuits is nowadays facing a downscale limitation. To overpass this nanoscale limit, modern transistors with complex geometries have flourished, allowing higher performance and energy efficiency. Accompanying this breakthrough, challenges toward high-performance devices have emerged on each significant step, such as the inhomogeneous coverage issue and thermal-induced short circuit issue of metal silicide formation. In this respect, we developed a two-step organometallic approach for nickel silicide formation under near-ambient temperature. Transmission electron and atomic force microscopy show the formation of a homogeneous and conformal layer of NiSix on pristine silicon surface. Post-treatment decreases the carbon content to a level similar to what is found for the original wafer (∼6%). X-ray photoelectron spectroscopy also reveals an increasing ratio of Si content in the layer after annealing, which is shown to be NiSi2 according to X-ray absorption spectroscopy investigation on a Si nanoparticle model. I-V characteristic fitting reveals that this NiSi2 layer exhibits a competitive Schottky barrier height of 0.41 eV and series resistance of 8.5 Ω, thus opening an alternative low-temperature route for metal silicide formation on advanced devices.

(001) 3C SiC/Ni contact interface: In situ XPS observation of annealing induced Ni2Si formation and the resulting barrier height changes

The electronic states of the (001) 3C SiC/Ni interface prior and post annealing are investigated via an in situ XPS interface experiment, allowing direct observation of the induced band bending and the transformation from Schottky to ohmic behaviour for the first time. A single domain (001) 3C SiC sample was prepared via wet chemical etching. Nickel was deposited on the sample in multiple in situ deposition steps via RF sputtering, allowing observation of the 3C SiC/Ni interface formation. Over the course of the experiments, an upward band bending of 0.35eV was observed, along with defect induced Fermi level pinning. This indicates a Schottky type contact behaviour with a barrier height of 0.41eV. The subsequent annealing at 850°C for 5min resulted in the formation of a Ni2Si layer and a reversal of the band bending to 0.06eV downward. Thus explaining the ohmic contact behaviour frequently reported for annealed n-type 3C SiC/Ni contacts.

Characterization and crystallization kinetics of sputtered NiSi thin films for blue laser optical recording application

In this study, Ni31Si69, Ni43Si57 and Ni63Si37 thin films with the thickness of 16 nm were deposited at room temperature by co-sputtering using Ni and Si targets. From the result of reflectivity-temperature measurement, it was found the NiSi layers possessed two temperature ranges of reflectivity change, i.e. 150–270 °C and 320–370 °C. Microstructural analysis indicated that the NiSi2 nano-crystalline phase was formed in the as-deposited state. After annealing at 270 and 500 °C, the crystallinity of NiSi2 phase was improved and the Ni2Si phase appeared, respectively. By measuring the optical reflectivity at a wavelength of 405 nm, the optical contrasts of these films before and after annealing at 270 °C were determined to be 24%, 16% and 26% with the Ni contents of 31, 43 and 63 at.%, respectively. The optimum jitter values of Ni31Si69 blu-ray disc were 7.7% at 5.7 mW and 8.2% at 7 mW, respectively, for 1× and 2× recording speeds. It reveals that the NiSi films have high potential in the application of blue laser recording media.

First stages of Ni reaction with the Si(Ge) alloy

The Si(Ge) alloy is currently used in the Complementary Metal Oxide Semiconductor (CMOS) technology, improving device performances, decreasing power consumption, and allowing stress engineering in Si-based devices. If Si(Ge) is used in transistors' source, drain and gate, it is necessary to create ohmic contacts between the first-level metal and Si(Ge). In the current Si-based CMOS technology, ohmic contacts are created via the reaction of a thin Ni(Pt) layer with doped-Si, aiming to form a thin NiSi layer on the Si substrate. A similar process should be used on Si(Ge). In this work, the first stages of Ni reaction with Si(Ge) is investigated using high resolution transmission electron microscopy and laser-assisted atom probe tomography. The first stage of Ni/Si(Ge) reaction leads to the formation of a germano-silicide layer made of Nip(Si1−xGex)q nano-grains exhibiting different structures and compositions. The formation of Nip(Si1−xGex)q phases occurs at temperatures as low as 60 °C. The germano-silicide grains exhibit coherent interfaces with the Si(Ge) layer, and during their growth, a fraction of the Ge atoms initially located in Si(Ge) is pushed from the Nip(Si1−xGex)q/Si(Ge) interface into the Si(Ge) layer, leading to Ge accumulation at this interface. This phenomenon can cause Ge accumulation up to 100%, promoting the incorporation of Ge-pure nanometric inclusions inside the germano-silicide layer.

Microstructural Evolution and Mechanical Properties of 2D–SiCf/SiC and Hastelloy N Joints Using 82.5Au–17.5Ni Brazing Filler

In this paper, SiC fiber reinforced SiC composite (SiCf/SiC) is joined to Hastelloy N alloy using 82.5Au–17.5Ni (wt%) foil as brazing filler. The microstructural evolution of the joints is investigated using scanning electron microscopy (SEM), energy dispersive spectrometry (EDS), X‐ray diffraction (XRD), and Raman spectroscopy. The shear strengths of the joints are tested by the mechanical testing machine. The results show the formation of nanocrystalline graphites, Ni2Si layer, and Ni31Si12 phases. With increasing temperature, Ni2Si is transformed gradually into Ni31Si12. The shear strength reaches a maximum value of 24.5 MPa when the joint is brazed at 1 000 °C for 30 min.