Neutron-induced Soft Error Research Articles

Fusion Neutron-Induced Soft Errors During Long Pulse D-D Plasma Discharges in the WEST Tokamak

Fusion Neutron-Induced Soft Errors During Long Pulse D-D Plasma Discharges in the WEST Tokamak

Investigating the reliability impacts of neutron-induced soft errors in aerial image classification CNNs implemented in a softcore SRAM-based FPGA GPU

This work investigates the impacts of neutron-induced soft errors on the reliability of aerial image classification neural networks running on a softcore GPU implemented in an SRAM-based FPGA. We designed and trained fixed-point and floating-point all-convolutional neural networks to classify four-channel aerial images from the SAT-6 dataset, extracted from the U.S. National Agriculture Imagery Program, and implemented on FGPU, a configurable open-source GPU-like processor with floating-point arithmetic hardware. Results from fast neutron and thermal neutron irradiation experiments coupled with configuration bitstream fault injection campaigns show that the impact of soft errors in the aerial image classification must be taken care of with hardening techniques.

Assessment of Tiny Machine-Learning Computing Systems Under Neutron-Induced Radiation Effects

This article compares and assesses the effectiveness of three prominent machine learning (ML) models for tiny ML computing systems in tolerating neutron-induced soft errors. Results of 14-MeV and thermal neutron radiation tests suggest that the three case-study ML algorithms implemented—without any mitigation technique integrated—retain a certain intrinsic level of effectiveness in tolerating neutron effects, although all of them have been functionally interrupted on some occasions, requiring hardware resets. Notably, the implemented case-study ML algorithm “random forest” has performed no misclassification during the different radiation testing campaigns.

Energy-Resolved Soft-Error Rate Measurements for 1–800 MeV Neutrons by the Time-of-Flight Technique at LANSCE

Problems caused by neutron-induced soft errors in electrical devices are becoming increasingly common in various applications. The neutron-energy-dependent soft-error rate is indispensable for evaluating the frequency of such errors in different neutron fields. We have observed the energy-dependent neutron-induced error rates continuously over the energy range of 1–800 MeV at Los Alamos Neutron Science Center (LANSCE). This was made possible by using extremely fast circuits built into field-programmable gate arrays (FPGAs) for time-of-flight measurement. Current experimental results revealed the overall trend of the error rate, which gradually increases up to 20 MeV. Interestingly, the rate depended on the type of device, and the errors occurred even below the threshold energy of the nuclear cross section of silicon, 2.75 MeV.

Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate

Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate

Accelerated Tests of Soft Errors in Network Systems Using a Compact Accelerator- Driven Neutron Source

The frequency of neutron-induced soft errors is increasing as devices become more integrated and miniaturized. Therefore, it has become more important recently to check reliability of a recovery system from the soft errors in network systems. For accelerated test, first we have examined possibility of the acceleration tests at a compact accelerator-driven neutron source, which is easy to adjust for soft-error tests and which also has low experimental costs. We selected the electron accelerator-driven neutron source at Hokkaido University as the compact accelerator-driven neutron source. We prepared a new target-reflector assembly composed of heavy metals to provide the fast neutrons, and conducted neutron-induced soft-error experiments on network equipments. As a result, we found that an accelerated rate of soft errors was about $10^{{\mathbf {6}}}$ times compared with that of the natural environment. We also investigated network equipment soft-error tolerance, fault detection and backup switching processes. Performing such testing before network equipment is actually deployed is critical for development of future network systems. Hence, the compact accelerator-based neutron source is a very useful tool.

Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations

This paper analyzes how body bias and BOX region thickness affect soft error rates in 65-nm SOTB (Silicon on Thin BOX) and 28-nm UTBB (Ultra Thin Body and BOX) FD-SOI processes. Soft errors are induced by alpha-particle and neutron irradiation and the results are then analyzed by Monte Carlo based simulation using PHITS-TCAD. The alpha-particle-induced single event upset (SEU) cross-section and neutron-induced soft error rate (SER) obtained by simulation are consistent with measurement results. We clarify that SERs decreased in response to an increase in the BOX thickness for SOTB while SERs in UTBB are independent of BOX thickness. We also discover SOTB develops a higher tolerance to soft errors when reverse body bias is applied while UTBB become more susceptible

Soft error rate analysis based on multiple sensitive volume model using PHITS

Secondary cosmic-ray neutron-induced soft errors in an n-type metal-oxide-semiconductor field-effect transistor are analyzed based on the multiple sensitive volume (MSV) model using Particle and Heavy Ion Transport code System (PHITS). The soft error rates (SERs) and the collected charge for each single event are compared with those obtained by PHits-HYenexss integrated code System for Effects of Radiation on Device (PHYSERD) based on the detailed technology computer-aided design (TCAD) simulation and by the single sensitive volume (SSV) model using PHITS. It is found that PHITS+MSV provides approximate SERs in a shorter time than PHYSERD by estimating collected charges without event-by-event TCAD simulation. Furthermore, PHITS+MSV reproduces collected charge for each single event more accurately than PHITS+SSV by considering spatial dependence of the charge collection efficiencies. Therefore, PHITS+MSV is the most suitable to estimate SERs in practical design of semiconductor devices which require high accuracy and a short computational time.

Impact of Nuclear Reaction Models on Neutron-Induced Soft Error Rate Analysis

Terrestrial neutron-induced soft error rate (SER) analyses in the 25-nm design rule MOSFET are performed by means of multiscale Monte Carlo simulation with different nuclear reaction models used in PHITS code. It is clarified that a choice of nuclear reaction models has a great effect on the SER prediction. Even if the calculated production cross sections for secondary ions are the same among different reaction models, the difference in double-differential cross sections results in essential impact on the calculated SERs. Through validation of the nuclear reaction models used in PHITS code, it is concluded that the combined use of the e-mode with JENDL-4.0 below 20 MeV and the MQMD plus GEM above 20 MeV is the most suitable for the soft error simulation.

Nuclear Reaction Models Responsible for Simulation of Neutron-induced Soft Errors in Microelectronics

Terrestrial neutron-induced soft errors in MOSFETs from a 65 nm down to a 25 nm design rule are analyzed by means of multi-scale Monte Carlo simulation using the PHITS-HyENEXSS code system. Nuclear reaction models implemented in PHITS code are validated by comparisons with experimental data. From the analysis of calculated soft error rates, it is clarified that secondary He and H ions provide a major impact on soft errors with decreasing critical charge. It is also found that the high energy component from 10 MeV up to several hundreds of MeV in secondary cosmic-ray neutrons has the most significant source of soft errors regardless of design rule.

Thermal Neutron-Induced Soft Errors in Advanced Memory and Logic Devices

Thermal neutron-induced soft errors (SERs) for memory and logic devices have reappeared as a reliability issue for advanced IC technologies due to the presence of the B10 isotope in B2H6 carrier gases used during manufacturing. Here, we show that thermal neutron SER significantly decreases with Si technology progression, becoming an insignificant contributor to overall circuit SER below the 28-nm technology node.

A Bayesian Reliability Analysis of Neutron-Induced Errors in High Performance Computing Hardware

A soft error is an undesired change in an electronic device's state, for example, a bit flip in computer memory, that does not permanently affect its functionality. In microprocessor systems, neutron-induced soft errors can cause crashes and silent data corruption (SDC). SDC occurs when a soft error produces a computational result that is incorrect, without the system issuing a warning or error message. Hence, neutron-induced soft errors are a major concern for high performance computing platforms that perform scientific computation. Through accelerated neutron beam testing of hardware in its field configuration, the frequencies of failures (crashes) and of SDCs in hardware from the Roadrunner platform, the first Petaflop supercomputer, are estimated. The impact of key factors on field performance is investigated and estimates of field reliability are provided. Finally, a novel statistical approach for the analysis of interval-censored survival data with mixed effects and uncertainty in the interval endpoints, key features of the experimental data, is presented. Supplementary materials for this article are available online.

Analysis of Interval-Censored Data with Random Unknown End Points: An Application to Soft Error Rate Estimation

Summary The paper presents a Bayesian approach to analysing interval-censored data with random unknown end points. Such data occur when the event of interest is interval censored but, because of the measurement process, the interval end points are not known exactly. Modelling the measurement process permits inference that accounts for this source of variability. Our results are motivated by an experimental study that was designed to characterize the cosmic-ray–neutron-induced soft error rate of a semiconductor device.

Temperature dependence of neutron-induced soft errors in SRAMs

We irradiated commercial SRAMs with wide-spectrum neutrons at different temperatures. We observed that, depending on the vendor, the soft error rate either increases or slightly decreases with temperature, even in devices belonging to the same technology node. SPICE simulations were used to investigate the temperature dependence of the cell feedback time and restoring current. The shape and magnitude of the particle-induced transient current is discussed as a function of temperature. The variability in the response is attributed to the balance of contrasting factors, such as cell speed reduction and increased diffusion with increasing temperature.

Experimental study of neutron-induced soft errors in modern cardiac pacemakers

Density of circuits and size reduction of microelectronic devices increase the sensitivity to natural terrestrial radiation environment. Atmospheric particles, mainly neutrons can cause non-destructive or destructive failures in most electronic circuits, including volatile static memories. The failure occurrence probability of a soft error in real life is very low. However, in the last few years, a safety alert had to be communicated to the physicians for a few defibrillator models potentially affected by background levels of atmospheric ionizing cosmic radiation. The aim of this study was to test in vitro a variety of currently available pacemakers exposed to experimental neutron irradiation. The neutron irradiation at high flux fast neutron beam was performed using Cyclone facility, with the cyclotron of the University of Leuven, Belgium. The neutron energy spectrum was obtained with a peak around 20 mega-electron volt (MeV) energy range from 3 to 50 MeV, and tests were performed at three fluence levels: 1E9, 5E9, and 1E10 neutrons/cm(2). A total of 14 tests were conducted on 14 devices from four manufacturers. Following the test, the devices were functioning normally in eight cases. In six cases, the response at interrogation was a message on the programmer screen announcing an electrical reset. In all of these cases, the programmer reset command was activated and immediately restored normal functioning and programmability. For a same model, the electrical reset was present at high fluence (1E10 or/and 5E9 n/cm²) and not at the lower level (1E9 n/cm²). Obvious differences among manufacturers were shown in this small sample study. This experiment shows the sensibility of modern pacemakers to neutron-induced soft errors and effectiveness of backup reversion in response to irradiation. The lower neutron fluence associated with a positive test was used to propose the calculation of the very low soft error rate for the tested devices in real-life atmospheric radiation.

Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits

Radiation-induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft-error rates (SERs) in combinational circuits. In this work, we present methodologies to model soft errors in both the device and logic levels. At the device level, a hierarchical methodology to model neutron-induced soft errors is proposed. This model is used to create a transient current library, which will be useful for circuit-level soft-error estimation. The library contains the transient current response to various different factors such as ion energies, operating voltage, substrate bias, angle, and location of impact. At the logic level, we propose a new approach to estimating the SER of logic circuits that attempts to capture electrical, logic, and latch window masking concurrently. The average error of the SER estimates using our approach, compared to the estimates obtained using circuit-level simulations, is 6.5 percent while providing an average speedup of 15,000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130nm, and 90nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

Neutron-induced soft error rate measurements in semiconductor memories

Soft error rate (SER) testing of devices have been performed using the neutron beam at the Radiation Science and Engineering Center at Penn State University. The soft error susceptibility for different memory chips working at different technology nodes and operating voltages is determined. The effect of 10B on SER as an in situ excess charge source is observed. The effect of higher-energy neutrons on circuit operation will be published later. Penn State Breazeale Nuclear Reactor was used as the neutron source in the experiments. The high neutron flux allows for accelerated testing of the SER phenomenon. The experiments and analyses have been performed only on soft errors due to thermal neutrons. Various memory chips manufactured by different vendors were tested at various supply voltages and reactor power levels. The effect of 10B reaction caused by thermal neutron absorption on SER is discussed.

Predicting Thermal Neutron-Induced Soft Errors in Static Memories Using TCAD and Physics-Based Monte Carlo Simulation Tools

A combination of commercial simulation tools and custom applications utilizing Geant4 physics libraries is used to analyze thermal neutron induced soft error rates in a commercial bulk CMOS SRAM. Detailed descriptions of the sensitive regions based upon technology in computer-aided design calibration are used in conjunction with a physics-based Monte Carlo simulator to predict neutron soft error cross sections that are in good agreement with experimental results