Neural Network Processing Research Articles

A high-efficiency spaceborne processor for hybrid neural networks

Featuring with characteristics of convolutional neural network (CNN) and recurrent neural network (RNN), hybrid neural network (H-NN) has been widely applied within the field of remote sensing. In order to satisfy de mands of on-orbit processing that requires high throughput with restriction on power consumption, designing specific heterogeneous array processor therefore becomes one of the most effective ways fulfilling various tasks engaged in the above field. In this paper, a heterogeneous array architecture is proposed to support the hybrid neural network, based on the characteristics of various computation types in between different neural network module types and of dynamic computation burden among different layers. Firstly, a heterogeneous array structure consisting of different PE, PPE, RPE and LPE units is proposed, enabling strong flexibility and high throughput. Four types of operation units are used for operations of MAC, ReLU, pooling and nonlinear lookup-table. Secondly, a multi-level on-chip memory structure and access strategy supporting different access modes are proposed to reduce the bandwidth requirements of off-chip data access and to improve the computation efficiency. Thirdly, a management strategy of heterogeneous computing array is designed, which combines pipelining and parallel processing to support efficient mapping of different types of hybrid neural networks. The hybrid neural network processor based on 65 nm CMOS technique has a peak throughput of up to 1.96 TOPS. The implementation on models of AlexNet, LRCN, VGG19-LSTM and CLDNN can achieve the throughput of 1.92 TOPS, 1.89 TOPS, 1.93 TOPS and 1.84 TOPS, respectively. Compared with the similar neural network processor that is based on the same technology, the throughput of AlexNet model is increased by 76.4%. The peak power consumption of a single processor core is 824mW, to which the power consumption restriction of on-orbit AI platform is satisfied.

TCX: A RISC Style Tensor Computing Extension and a Programmable Tensor Processor

Neural network processors and accelerators are domain-specific architectures deployed to solve the high computational requirements of deep learning algorithms. This article proposes a new instruction set extension for tensor computing, TCX, using Reduced Instruction Set Computer (RISC) instructions enhanced with variable length tensor extensions. It features a multi-dimensional register file, dimension registers, and fully generic tensor instructions. It can be seamlessly integrated into existing RISC Instruction Set Architectures and provides software compatibility for scalable hardware implementations. We present a tensor accelerator implementation of the tensor extensions using an out-of-order RISC microarchitecture. The tensor accelerator is scalable in computation units from several hundred to tens of thousands. An optimized register renaming mechanism is described that allows for many physical tensor registers without requiring architectural support for large tensor register names. We describe new tensor load and store instructions that reduce bandwidth requirements using tensor dimension registers. Implementations may balance data bandwidth and computation utilization for different types of tensor computations such as element-wise, depthwise, and matrix-multiplication. We characterize the computation precision of tensor operations to balance area, generality, and accuracy loss for several well-known neural networks. The TCX processor runs at 1 GHz and sustains 8.2 Tera operations per second using a 4,096 multiply-accumulate compute unit. It consumes 12.8 mm 2 while dissipating 0.46W/TOPs in TSMC 28-nm technology.

Infomax-based deep autoencoder network for recognition of multi-element geochemical anomalies linked to mineralization

In recent years, deep autoencoder networks (DANs) have shown enormous potential to achieve state-of-the-art performance for recognizing multi-element geochemical anomalies related to mineralization. By training a DAN, multi-element signatures of geochemical background are learned by higher-level representations of input signals, providing key references to quantify reconstruction errors linked to complex patterns of metal-vectoring geochemical anomalies in non-linear Earth systems. However, the learning of geochemical background representations may be suppressed by redundant mutual information from inter-element correlations and by mixed information of elemental concentration data caused by multiplicative cascade geo-processes. To deal with these issues, we conceptualized an idea of a new deep learning architecture called Info‒DAN, chaining the information maximization (Infomax) processor to the training network of stacked autoencoders. Infomax is an adaptive learning algorithm from information theory paradigms which aims at maximizing the information flow (joint entropy) passed through a feed-forward neural network processor. It was adopted to encode original multi-element data into independent source signals associated with different geochemical sub-populations and to prevent the dilution of background representations caused by inter-element information redundancy. The recovered source signals were then fed into a DAN processor to assist in modeling the improved representations of geochemical background populations and in enhancing complex anomaly patterns. The Info‒DAN technique was applied to stream sediment geochemical data pertaining to the Moalleman district, NE Iran, for performance appraisal in recognition of metal-vectoring geochemical anomalies. Evaluation tools comprising success-rate curves and prediction-area plots indicated that anomaly patterns derived from Info‒DAN, compared to those from a stand-alone DAN, reveal a stronger spatial correlation between ore-controlling fractures/faults and locations of known metal occurrences. The findings suggest that, thanks to the proposed algorithm, complex patterns of geochemical anomalies can be quantified with improved generalization accuracy as well as practical insights for vectoring towards metal exploration targets.

Machine Learning‐Derived Inference of the Meridional Overturning Circulation From Satellite‐Observable Variables in an Ocean State Estimate

AbstractThe oceanic Meridional Overturning Circulation (MOC) plays a key role in the climate system, and monitoring its evolution is a scientific priority. Monitoring arrays have been established at several latitudes in the Atlantic Ocean, but other latitudes and oceans remain unmonitored for logistical reasons. This study explores the possibility of inferring the MOC from globally‐available satellite measurements via machine learning (ML) techniques, using the ECCOV4 state estimate as a test bed. The methodological advantages of the present approach include the use purely of available satellite data, its applicability to multiple basins within a single ML framework, and the ML model simplicity (a feed‐forward fully connected neural network (NN) with small number of neurons). The ML model exhibits high skill in MOC reconstruction in the Atlantic, Indo‐Pacific, and Southern Oceans. The approach achieves a higher skill in predicting the model Southern Ocean abyssal MOC than has previously been achieved via a dynamically‐based approach. The skill of the model is quantified as a function of latitude in each ocean basin, and of the time scale of MOC variability. We find that ocean bottom pressure generally has the highest reconstruction skill potential, followed by zonal wind stress. We additionally test which combinations of variables are optimal. Furthermore, ML interpretability techniques are used to show that high reconstruction skill in the Southern Ocean is mainly due to (NN processing of) bottom pressure variability at a few prominent bathymetric ridges. Finally, the potential for reconstructing MOC strength estimates from real satellite measurements is discussed.

Algorithm for detection of moving objects observed by a video camera

An algorithm to detect moving objects captured by a moving video camera is presented. The algorithm is based on detection of motion on video frames taken by a moving video camera, as well as on finding and analyzing the trajectories of moving objects. A feature of the algorithm is detection on frames of connected areas (clusters) of possible object motion. Then moving points on the detected clusters are found, and those points trajectories are built with help of the optical flow. The trajectories are used as features of moving objects. Only smooth trajectories are exploited for detection of moving objects, and the remaining ones are removed from consideration. An object is considered as moving on the current frame if it contains ends of a sufficient number of trajectories of moving points found on previous frames. The presented algorithm has a low computational complexity, which allows it to be used in real or near real time on small computers that have only a few processors of the ARM architecture without powerful parallel computing tools such as GPUs or neural network processors NPU.

Universal Linear Optics Revisited: New Perspectives for Neuromorphic Computing With Silicon Photonics

Reprogrammable optical meshes comprise a subject of heightened interest for the execution of linear transformations, having a significant impact in numerous applications that extend from the implementation of optical switches up to neuromorphic computing. Herein, we review the state-of-the-art approaches for the realization of unitary transformations and universal linear operators in the photonic domain and present our recent work in the field, that allows for fidelity restorable and low-loss optical circuitry with single-step programmability. These advantages unlock a new framework for matrix-vector multiplications required by neuromorphic silicon photonic circuits, supporting: i) high-speed and high-accuracy neural network (NN) inference, ii) high-speed tiled matrix multiplication, iii) NN training and iv) programmable photonic NNs. This new potential is initially validated through recent experimental results using SiGe EAM technology and static weights and, subsequently, utilized for demonstrating experimentally the first Deep NN (DNN) where optical tiled matrix multiplication up to 50 GHz is realized, allowing optics to execute DNNs with large number of trainable parameters over a limited photonic hardware. Finally, the new performance framework is benchmarked against state-of-the-art NN processors and photonic NN roadmap projections, highlighting its perspectives to turn the energy and area efficiency promise of neuromorphic silicon photonics into a tangible reality.

A 915–1220 TOPS/W, 976–1301 GOPS Hybrid In-Memory Computing Based Always-On Image Processing for Neuromorphic Vision Sensors

Neuromorphic vision sensors (NVSs) save energy and reduce data at the source by asynchronously recording changes in temporal contrast. Thus, NVS provides an opportunity to exploit temporal and spatial redundancy in video streams by enabling the following deep neural network (DNN) processor for object recognition to process only foreground object regions in valid frames. However, the NVS data inevitably contains noise leading to false frame generation. Moreover, objects may be fragmented due to a lack of events leading to wrong object region proposals (RPs). Hence, it is important to have an always ON image processor to perform image restoration (IR) and RP operations for NVS data. In this article, we propose a hybrid memory bitcell with collocated static random access memory (SRAM) and dynamic random access memory (DRAM) consisting of 11 transistors [11T-collocated SRAM and DRAM (CRAM)] to perform in-memory computing (IMC)-based IR and RP for event-based binary image (EBBI) frame from a stationary NVS. We propose IMC-based charge diffusion for IR (denoise and region filling) by enabling a 2-D interconnection of bitcells across the whole array for globally parallel computing. The proposed CRAM supports projection mode for IMC-based RP, which enables 1-D projection of objects on the horizontal and vertical axes and finds regions through a recently proposed iterative algorithm. We also proposed an RP update (RPU) algorithm and hardware to improve RP accuracy by 1.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> over the prior art. Implemented in 65 nm CMOS, the 320 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 240 quarter video graphics array (QVGA) macro achieves a maximal energy efficiency (throughput) of 1220 TOPS/W (1301 GOPS) without RPU and 915 TOPS/W (976 GOPS) with RPU, both of which are superior to the prior art. We also show that the accuracy of IR and RP obtained by the proposed architecture is better than earlier methods.

Short-Term Forecasting of Power Consumption of Power Supply Companies Based on the Integration of Technologies of Analytical, Simulation and Expert Systems

Purpose of research is to improve software support and identify regularities in the processes of short-term forecasting of power consumption of power supply companies based on complementary integration of data mining models, system dynamics and expert systems.Methods. The principles of constructing predictive models of power consumption are given. A system analysis has been carried out and an ontological model of the subject area has been built, taking into account the technological and market environment. The classification of forecasting methods has been considered. The features of the information base for short-term forecasting, including data on actual power consumption and weather data, have been described. The requirements for software for making forecasts have been formulated. A block diagram of the system for forecasting power consumption of the market for the day ahead is built based on the complementary integration of data analysis and modeling software.Results. Scenarios for data processing in Loginom have been developed using the Arimax and Neural Network (Regression) processors to build forecasts based on actual power consumption and taking into account meteorological factors. A system dynamics simulation model that allows exploring the influence of meteorological factors (temperature, pressure, precipitation) on power consumption has been developed in Anylogic. Using Wi!Mi mivar constructor of expert systems, the task has been parametrized; indicators, relationships, rules have been set; a logical conclusion of the solution has been obtained.Conclusion. A block diagram of a system for forecasting the market's power consumption for the day ahead has been built. It is based on the analysis of retrospective information on actual power consumption and meteorological factors using data mining methods, system dynamics and expert systems applying Russian Loginom, Anylogic and Wi!Mi software tools.

Computer Vision Algorithm for the detection of fracture cracks in Oil Hardening Non-Shrinking (OHNS) die steel after machining process

A variant of neural network for processing with images is a convolutional neural network (CNN). This type of neural network receives input from an image and extracts features from the image while also providing learnable parameters to effectively do the classification, detection, and many other tasks. In the present work, U-Net convolutional neural network is implemented on Jupyter platform by using Python programming for fracture surface image segmentation in Oil Hardening Non-Shrinking (OHNS) die steel after the machining process. The results showed that the fracture cracks can be validated by testing with higher accuracy.

FQA-Net: an efficient neural network for blind image quality assessment

Guided by the neural network (NN), NN-based blind image quality assessment (BIQA) methods have improved image quality prediction accuracy. However, the training process of NN will consume a lot of time and training data. To solve the above problems, an efficient NN structure, which is called fast quality assessment network (FQA-Net), is proposed for BIQA. FQA-Net is a very simple NN, which mainly includes a convolution layer, a standard deviation measurement layer, and a regression layer. The convolution kernels in the convolution layer are a set of visual filters with characteristics of visual neurons, which are obtained by training on natural image samples. The output of the convolutional layer is a set of feature maps. Then the standard deviation of each feature map is calculated directly. Finally, a regression model is used for the mapping between the standard deviation values and the quality scores. FQA-Net not only reduces the number of parameters and the output dimensions in the training process, but also prevents network overfitting effectively. The results on seven image databases (i.e., LIVE, CSIQ, TID2013, LIVEMD, KADID-10K, LIVEC, and KonIQ-10K) show that FQA-Net has relatively low computational complexity and high computational speed and accuracy compared with other leading BIQA methods, especially when the number of training samples is very low. Moreover, the FQA-Net can provide stable prediction results across different distortion types.

Study of the kinetics, mechanisms and catalysis activity of photo-electro degradation of organic pollutants via new neural network based methodology

A novel calculation methodology containing modeling and statistics was developed to assist the experimental process for the investigation of organics treatment process. A continuous-flow photo-electro treatment of Norfloxacin (NOR) was chosen as a target subject. The methodology is based on a new synergistic work of reaction energy calculation, full-scanned neural network (NN) simulation and new physical kinetics modeling. Degradation kinetics, mechanisms and activity of degradation catalyst, etc., were studied. As a result, the reaction energy calculation figured out eight potential degradation pathways of NOR with the corresponding intermediate. NN process with fully scanned parameters showed dominating advantage compared to non-linear regression and first-order law in simulation work. With the obtained database from NN, the new physical model successfully distributed degradation contribution into direct, indirect and water flow routes. The new methodology helped to gain more valuable information with less experimental work, which guided the efficient and greener investigation process in corresponding studies.

GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy

Recurrent Neural Networks (RNNs) have emerged as one of the most popular neural networks for processing time-series problems, widely used in machine translation, automatic speech recognition, and other natural language processing applications. However, conventional RNNs suffered from vanishing and exploding gradients, resulting in poor network performance in applications with long-term input information. As a variant of RNN, Long Short-Term Memory (LSTM) had been proposed to tackle this issue. Nevertheless, at the same time, LSTM introduces gating units and many additional parameters, which makes it challenging to be implemented directly on resource-limited platforms, such as Field Programmable Gate Arrays (FPGAs). This work first investigated the overall maximum achievable compression rates of different gating units and their correlations. Then, Gating Units Level Balanced Compression (GBC) strategy is proposed. After Top- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> pruning, the proposed GBC strategy can attain a compression rate of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$36.6\times $ </tex-math></inline-formula> for LSTM. Further, the theoretical analysis indicates that for the existing gating units level LSTM compression variants, the GBC strategy still has further potential for compression. A complementary compression of the GBC strategy is performed on the existing coupled-gate LSTM to verify the analysis. Experimental results show that GBC achieves an additional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32\times $ </tex-math></inline-formula> (overall <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42.7\times $ </tex-math></inline-formula> ) compression rate with negligible accuracy loss. Finally, hardware experiments conducted on Xilinx ADM-PCIE-7V3 FPGAs also demonstrate that the accelerator designed in this paper achieves an improvement of 7.4%-191.5% in energy efficiency compared to the state-of-the-art designs.

Design of Convolutional Neural Network Processor Based on FPGA Resource Multiplexing Architecture.

As CNNs are widely used in fields such as image classification and target detection, the total number of parameters and computation of the models is gradually increasing. In addition, the requirements on hardware resources and power consumption for deploying CNNs are becoming higher and higher, leading to CNN models being restricted to certain specific platforms for miniaturization and practicality. Therefore, this paper proposes a convolutional-neural-network-processor design with an FPGA-based resource-multiplexing architecture, aiming to reduce the consumption of hardware resources and power consumption of CNNs. First, this paper takes a handwritten-digit-recognition CNN as an example of a CNN design based on a resource-multiplexing architecture, and the prediction accuracy of the CNN can reach 97.3 percent by training and testing with Mnist dataset. Then, the CNN is deployed on FPGA using the hardware description language Verilog, and the design is optimized by resource multiplexing and parallel processing. Finally, the total power consumption of the system is 1.03 W and the power consumption of the CNN module is 0.03 W under the premise of guaranteeing the prediction accuracy, and the prediction of a picture is about 68,139 clock cycles, which is 340.7 us under a 200 MHz clock. The experimental results have obvious advantages in terms of resources and power consumption compared with those reported in related articles in recent years, and the design proposed in this paper.

A Neuromorphic Processing System With Spike-Driven SNN Processor for Wearable ECG Classification.

This paper presents a neuromorphic processing system with a spike-driven spiking neural network (SNN) processor design for always-on wearable electrocardiogram (ECG) classification. In the proposed system, the ECG signal is captured by level crossing (LC) sampling, achieving native temporal coding with single-bit data representation, which is directly fed into an SNN in an event-driven manner. A hardware-aware spatio-temporal backpropagation (STBP) is suggested as the training scheme to adapt to the LC-based data representation and to generate lightweight SNN models. Such a training scheme diminishes the firing rate of the network with little plenty of classification accuracy loss, thus reducing the switching activity of the circuits for low-power operation. A specialized SNN processor is designed with the spike-driven processing flow and hierarchical memory access scheme. Validated with field programmable gate arrays (FPGA) and evaluated in 40 nm CMOS technology for application-specific integrated circuit (ASIC) design, the SNN processor can achieve 98.22% classification accuracy on the MIT-BIH database for 5-category classification, with an energy efficiency of 0.75 μJ/classification.

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse

Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) processors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated system integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utilization and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power-OFF ADCs is implemented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN models. The macro/system-level energy efficiency is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.23\times / 3.06\times $ </tex-math></inline-formula> higher compared with the state-of-the-art CIM macros and processors.

A Model of a Universal Neural Computer with Hysteresis Dynamics for Avionics Problems

The paper proposes a method for implementing a universal neural network processor with hysteresis dynamics. This processor allows a wide range of heterogeneous tasks in real time to be performed without reprogramming and changing their internal structure. Adding hysteresis behavior to the system makes it possible to increase resistance to external influences, the complexity as well as non-linearity of intelligent output. The paper discusses the use of this processor as part of an on-board intelligent avionics system.

Robust control for a class of nonlinear systems with input constraints based on actor‐critic learning

AbstractThis article focuses on establishing a general robust actor‐critic online learning control structure for disturbed nonlinear continuous systems with input constraints. It enriches the existing studies for the robustness of input constraint systems. First, the problem of robust controller design is successfully transformed into optimal controller design, and this process is proven, in which a particular nonquadratic discount cost function is defined. Then, build two neural networks (NNs) to estimate the cost function together and update each other. In the update process of actor NN, a robust term related to the state is introduced, which can guarantee the system's stability during the online learning process, and the state information is more fully utilized. Furthermore, using Lyapunov's direct method, it is proved that the estimated weights of the closed‐loop optimal control system and the actor‐critic NNs are uniformly ultimately bounded (UUB). It also provides extended discussions and a simulation example to demonstrate the robustness verification results of the novel algorithm.

Early Termination Based Training Acceleration for an Energy-Efficient SNN Processor Design.

In this paper, we present a novel early termination based training acceleration technique for temporal coding based spiking neural network (SNN) processor design. The proposed early termination scheme can efficiently identify the non-contributing training images during the training's feedforward process, and it skips the rest of the processes to save training energy and time. A metric to evaluate each input image's contribution to training has been developed, and it is compared with pre-determined threshold to decide whether to skip the rest of the training process. For the threshold selection, an adaptive threshold calculation method is presented to increase the computation skip ratio without sacrificing accuracy. Timestep splitting approach is also employed to allow more frequent early termination in split timesteps, thus leading to more computation savings. The proposed early termination and timestep splitting techniques achieve 51.21/42.31/93.53/30.36% reduction of synaptic operations and 86.06/64.63/90.82/49.14% reduction of feedforward timestep for the training process on MNIST/Fashion-MNIST/ETH-80/EMNIST-Letters dataset, respectively. The hardware implementation of the proposed SNN processor using 28 nm CMOS process shows that the SNN processor achieves the training energy saving of 61.76/31.88% and computation cycle reduction of 69.10/36.26% on MNIST/Fashion-MNIST dataset, respectively.

An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost.

The computation efficiency and flexibility of the accelerator hinder deep neural network (DNN) implementation in embedded applications. Although there are many publications on deep neural network (DNN) processors, there is still much room for deep optimization to further improve results. Multiple dimensions must be simultaneously considered when designing a DNN processor to reach the performance limit of the architecture, including architecture decision, flexibility, energy efficiency, and silicon cost minimization. Flexibility is defined as the ability to support as many multiple networks as possible and to easily adjust the scale. For energy efficiency, there are huge opportunities for power efficiency optimization, which involves access minimization and memory latency minimization based on on-chip memory minimization. Therefore, this work focused on low-power and low-latency data access with minimized silicon cost. This research was implemented based on an ASIP (application specific instruction set processor) in which an ISA was based on the caffe2 inference operator and the hardware design was based on a single instruction multiple data (SIMD) architecture. The scalability and system performance of our SoC extension scheme were demonstrated. The VLIW was used to execute multiple instructions in parallel. All costs for data access time were thus eliminated for the convolution layer. Finally, the processor was synthesized based on TSMC 65 nm technology with a 200 MHz clock, and the Soc extension scheme was analyzed in an experimental model. Our design was tested on several typical neural networks, achieving 196 GOPS at 200 MHz and 241 GOPS/W on the VGG16Net and AlexNet.

Direct estimation of gas holdup in gas–liquid bubble column reactors using ultrasonic transmission tomography and artificial neural processing

Ultrasonic transmission tomography is an effective non-intrusive method for detecting gas–liquid two-phase flow patterns. A specific interest is the many processes whose reaction utilizes a bubble column, where the fast estimation of cross-sectional gas-holdup ratio is important for monitoring and control. In this study reference indirect image-based estimates were obtained from reconstructed tomographic data. Direct (non-image) estimation of the gas holdup ratio was also obtained using trained neural processing networks. Two forms were trialled: a generalized regression neural network (GRNN); and a long short-term memory (LSTM) network. Comparison trials were carried out for single-bubble, dual-bubble, circulation and laminar flows. Relative cross-sectional gas holdup error was selected for evaluation. For the image-based indirect trials the Tikhonov regularization algorithm had the lowest error range: 2.15%–15.64%. For direct methods the LSTM network had the lowest error range: 0.41%–9.63%, giving better performance than the image-based methods. The experimental data were used to verify the effectiveness of the network. The root-mean-square error of the test metrics for GRNN and LSTM network were 6.4260 and 5.4282, respectively, indicating that LSTM network has higher performance in processing the data in this paper.