Network Processor Architecture Research Articles

Data compression algorithms for flow tables in Network Processor RuNPU

This paper addresses the problem of packet classification within a network processor (NP) architecture without the separate associative device. By the classification, we mean the process of identifying a packet by its header. The classification stage requires the implementation of data structures to store the flow tables. In our work, we consider the NP without the associative memory. Flow tables are represented by an assembly language program in the NP. For translating flow tables into assembly language programs, a tables translator was used. The main reason for implementing data compression algorithms in a flow tables translator is that modern flow tables can take up to tens of megabytes. In this paper, we describe the following data compression algorithms: Optimal rule caching, recursive end-point cutting and common data compression algorithms. An evaluation of the implemented data compression algorithms was performed on a simulation model of the NP.

A High-Throughput Network Processor Architecture for Latency-Critical Applications

This article presents the recent advancements on the Advanced IO Processor (AIOP), a network processor architecture designed by NXP Semiconductors. The AIOP is a multicore accelerated computing architecture where each core is equipped with dedicated hardware for rapid task switching on every hardware accelerator call. A hardware preemption controller snoops on the accelerator completions and sends task preemption requests to the cores, thus reducing the latency of real-time tasks. A technique of priority thresholding is used to avoid latency uncertainty on lower priority tasks and head-of-line blocking. In this way, the AIOP handles the conflicting requirements of high throughput and low latency for next-generation wireless applications such as WiFi and 5G. In presence of frequent preemptions, the throughput reduces by only 3% on AIOP, compared to 25% on a similar network processor. Moreover, the absolute throughput and latency numbers are 2X better. The area and power overhead of adding hardware task-scheduling and preemption is only about 3%.

CNNP-v2: A Memory-Centric Architecture for Low-Power CNN Processor on Domain-Specific Mobile Devices

An energy-efficient memory-centric convolutional neural network (CNN) processor architecture is proposed for smart devices such as wearable devices or the internet of things (IoT) devices. To achieve energy-efficient processing, it has two key features: First, 1-D shift convolution PEs with fully distributed memory architecture achieve 1.5TOPS/W energy efficiency, and it can be boosted up equivalent 3.1TOPS/W energy efficiency with separable filter approximation and transpose-read SRAM. Compared with conventional architecture, even though it has massively parallel 1024 MAC units, it achieves high energy efficiency by scaling down the voltage to 0.46V due to its fully local routed design. Second, fully configurable 2-D mesh core-to-core interconnection support the various size of input features to maximize utilization. The proposed architecture is evaluated 16mm2 chip, which is fabricated with a 65nm CMOS process. As a result, it performs real-time face recognition with the only 68.9mW at 40MHz and 0.6V.

An Approach to the Construction of a Network Processing Unit

The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.

Network processor architecture with flow-based dynamic bandwidth control for efficient QoS provisioning

This paper presents a network processor architecture with a flow-based dynamic bandwidth control method to efficiently provide QoS on ethernet. The proposed bandwidth control method identifies the active flows. The active flows’ incoming traffic is controlled by the limited bandwidth dynamically assigned to each active flow. NS2 simulation results show that the proposed method provides efficient QoS provisioning. Also, we designed and implemented a network processor with the proposed bandwidth control method. Then, an emulation board was developed using the implemented network processor and a physical layer ASIC chip. Finally, we evaluated the QoS provisioning performance of the network processor using the emulation board.

Providing Performance Guarantees in Multipass Network Processors

Current network processors (NPs) increasingly deal with packets with heterogeneous processing times. In such an environment, packets that require many processing cycles delay low-latency traffic because the common approach in today's NPs is to employ run-to-completion processing. These difficulties have led to the emergence of the Multipass NP architecture, where after a processing cycle ends, all processed packets are recycled into the buffer and recompete for processing resources. In this paper, we provide a model that captures many of the characteristics of this architecture, and we consider several scheduling and buffer management algorithms that are specially designed to optimize the performance of multipass network processors. In particular, we provide analytical guarantees for the throughput performance of our algorithms. We further conduct a comprehensive simulation study, which validates our results.

Creating portable and efficient packet processing applications

Network processors are special-purpose programmable units deployed in many modern high-speed network devices, which combine flexibility and high performance. However, software development for these platforms is traditionally cumbersome due both to the lack of adequate programming abstractions and to the impossibility of reusing the same software on different hardware platforms. In this context, the Network Virtual Machine (NetVM) aims at defining an abstraction layer for the development of portable and efficient data-plane packet processing applications. Portability and efficiency are achieved altogether by virtualizing the hardware and by capturing in the programming model the peculiar characteristics of the application domain. This paper validates the NetVM model, demonstrating that the proposed abstraction coupled with a proper implementation of the NetVM Framework is able to provide generality (i.e., capability to support a wide range of applications), software portability across heterogeneous network processor architectures, and efficiency of the generated code, often exceeding the one obtained using state-of-the-art compilers.

글로벌 캐시를 이용한 네트워크 병렬 프로세서 구조 연구

The mount of network traffic from the Internet is increasing because of the use of Broadband Convergence Networks(BcN). Network traffic is also increasing because of the development of application, especially multimedia traffic from IPTV, VOD, and online games. This multimedia traffic not only has a huge payload but also should be considered a threat in real time. For this reason, this study examines the ways that routers distribute the bandwidth in accordance to traffic properties. To classify the property of the traffic, it is essential to analyze the application layer. However, the general network processor architecture serially processes the L2-4 and L7 layer. We propose a novel parallel network processor architecture with a global cache that processes L2-4 and L7 in parallel. To verify the proposed architecture, we simulated both of the architecture with SystemC. EEMBC and SNORT was used to measure L2-4 and L7 processing time. When multimedia traffic was entered into the network processor in the same flow, the proposed architecture showed about 85% higher performance than general architecture.

VPN Gateways over Network Processors: Implementation and Evaluation

Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII 1GHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.

Efficiency of Cache Mechanism for Network Processors

With the explosion of network bandwidth and the ever-changing requirements for diverse network-based applications, the traditional processing architectures, i.e., general purpose processor (GPP) and application specific integrated circuits (ASIC) cannot provide sufficient flexibility and high performance at the same time. Thus, the network processor (NP) has emerged as an alternative to meet these dual demands for today's network processing. The NP combines embedded multi-threaded cores with a rich memory hierarchy that can adapt to different networking circumstances when customized by the application developers. In today's NP architectures, multithreading prevails over cache mechanism, which has achieved great success in GPP to hide memory access latencies. This paper focuses on the efficiency of the cache mechanism in an NP. Theoretical timing models of packet processing are established for evaluating cache efficiency and experiments are performed based on real-life network backbone traces. Testing results show that an improvement of nearly 70% can be gained in throughput with assistance from the cache mechanism. Accordingly, the cache mechanism is still efficient and irreplaceable in network processing, despite the existing of multithreading.

Analytic modeling of network processors for parallel workload mapping

Network processors are heterogeneous system-on-chip multiprocessors that are optimized to perform packet forwarding and processing tasks at Gigabit data rates. To meet the performance demands of increasing link speeds and complex network applications, network processors are implemented with several dozen embedded processor cores and hardware accelerators that run multiple packet processing applications in parallel. The parallel nature of the processing system makes it increasingly difficult for application developers to understand and manage resources and map processing tasks to the hardware. To address this problem, we present a methodology for profiling and analyzing network processor applications, mapping processing tasks to a generalized network processor architecture, and analytically determining the expected throughput performance. The key novelty of this work is not only the adaptation of application analysis and mapping algorithms to heterogeneous network processors, but also that the entire process can be automated and hidden from the application developer. Starting with the analysis of a uniprocessor implementation of the application, the process yields a mapping of the partitioned application that shows best performance for a given network processor system. The simplicity of the proposed randomized mapping algorithm allows the use of this methodology in network processor runtime systems where dynamic reallocation of tasks is necessary but processing power is limited. We present results that show the effectiveness of the analysis and mapping methodology as well as its application to design space exploration.

In-Network Adaptation of Video Streams Using Network Processors

The increasing variety of networks and end systems, especially wireless devices, pose new challenges in communication support for, particularly, multicast-based collaborative applications. In traditional multicasting, the sender transmits video at the same rate and resolution to all receivers independent of their network characteristics, end system equipment, and users' preferences about video quality and significance. Such an approach results in resources being wasted and may also result in some receivers having their quality expectations unsatisfied. This problem can be addressed, near the network edge, by applying dynamic, in-network adaptation (e.g., transcoding) of video streams to meet available connection bandwidth, machine characteristics, and client preferences. In this paper, we extrapolate from earlier work of Shorfuzzaman et al. 2006 in which we implemented and assessed an MPEG-1 transcoding system on the Intel IXP1200 network processor to consider the feasibility of in-network transcoding for other video formats and network processor architectures. The use of “on-the-fly” video adaptation near the edge of the network offers the promise of simpler support for a wide range of end devices with different display, and so forth, characteristics that can be used in different types of environments.

ILP and heuristic techniques for system-level design on network processor architectures

Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic

A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.

A Hybrid Network Processor with Support for High-Speed Execution of CPN and Upper Layer IP Protocols

The trend in network processing is towards layer 4-7 processing in the routers and switches. In this paper, we present a hybrid network processor (NPU) architecture that supports high-speed execution of higher layer TCP/IP protocol processing. The architecture achieves this by employing optimized logic blocks for specific tasks in the processing elements. This is a unique architecture such that it can realize both task-level and packet-level parallelism. We also present an example of implementation of a fast adaptive routing algorithm, Cognitive Packet Networks (CPNs), using the proposed NPU architecture. CPN uses a neural network model with a reinforcement learning algorithm to find routes. The applicability of the CPN concept has been demonstrated through several software implementations. Through hardware implementation, we show that this new network model can sustain similar line rates as the current IP protocols.

TAPES—Trace-based architecture performance evaluation with SystemC

The design of today's System-on-Chip (SoC) architectures faces many challenges in respect to the involved complexity and heterogeneity. An early and systematic exploration of alternatives is mandatory to find a solution that meets all design requirements. Therefore, the experience of system architects has to be supplemented with efficient performance evaluation methods and tools that help in the broad exploration of the solution space. This article describes TAPES (Trace-based Architecture Performance Evaluation with SystemC), an approach that supports system designers in the performance evaluation of SoC architectures. The concept captures the functionality of the architecture in the form of traces for each resource. The trace primitives making up a trace are translated at simulation run-time into transactions and superposed on the system architecture. The method uses SystemC as modeling language, requires low modeling effort and yet provides accurate results within reasonable turnaround times. A concluding application example for the exploration of a network processor architecture demonstrates the effectiveness of the TAPES approach.

Parallel Processing in Network Processor Architectures (Parallelverarbeitung in Netzwerkprozessorarchitekturen)

Summury Parallel processing is well established in high-performance computing. Currently, network processors as new emerging, special-purpose processors are targeted at the exploitation of parallelism to meet the requirements in data-plane processing with wire-speed. The achievable level of parallelism is determined by decisions in the architecture design and by the characteristics of the data-plane applications executed. We discuss two basic approaches in parallel processing, namely pipelining and concurrency, which establish basic models for parallel network processor organization. The features and constraints of these models are studied. Using this background some existing network processor architectures are reviewed and characterized regarding their potential in parallel data-plane processing.

Assertion Based Verification and Analysis of Network Processor Architectures

System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific designs. To make sure that the executable models behave as they should, the designers often have to "eye-ball" the simulation traces and at best, apply simple "assert" statements or write simple trace checkers in some scripting languages. The problem is the lack of a concise and formal method to specify and check desired properties, whether they be functional or performance in nature. In this paper, we apply assertion checking methodology to the system design of network processors. Functional and performance assertions, based on Linear Temporal Logic and Logic of Constraints, are written during the design process. Trace checkers and simulation monitors are automatically generated to validate particular simulation runs or to analyze their performance characteristics. Several categories of assertions are checked throughout the design process, such as equivalence, functionality, transaction, and performance. We demonstrate that the assertion-based methodology is very useful for both system level verification and design exploration.

Speeding up high-speed protocol processors

Many network technologies aim to exploit the bandwidth of high-speed links, which now achieve data transfer rates up to several terabits per second. As packet interarrival times shrink to a few tens of nanoseconds, network systems must address a transmission-processing gap by providing extremely fast data paths as well as high-performance subsystems to implement such functions as protocol processing, memory management, and scheduling. Today, network processors are an important class of embedded processors, used all across the network systems space-from personal to local and wide area networks. Network processor architectures focus on exploiting parallelism to achieve high performance. They usually employ conventional architectural concepts to accelerate the processing required to switch packets between different protocol stacks. The architectures support the mechanisms that network protocols implement in a specific stack by providing efficient data paths and by executing many intelligent network or more homogeneous links - for example, a set of Ethernet links. Although network processors can also handle packets concurrently from different protocol stacks, we describe only single-stack processing here. However, the arguments and results extend to a multistack environment.

Network processor requirements and benchmarking

This paper intends to explore the demands put on Network Processors by evaluating their claim to address adequately the needs of Broadband Integrated Services Digital Networks, based on variable length packet communication. It starts by giving an overview of the elementary functions that are seen as essential capabilities to cover the broadening spectrum of packet communication applications. Besides functionality, performance is also critical in modern packet-based communication networks, not only for performing the elementary functions in isolation, but particularly for combinations of functions, to be executed by a Network Processor in the presence of live traffic, in a true contemporary network environment. The discussion of the requirements imposed by the external world is complemented by a brief overview of needs forthcoming from inter-working with another technologically demanding part of a packet network node: the switch fabric. Requirements for functionality and performance are one thing. The capability to meet them is another. The third part of the paper will discuss the strengths and weaknesses of some possible Network Processor architectures, when trying to meet these requirements. Aspects like packet classification, packet editing, data store access, packet scheduling and packet segmentation and re-assembly for cell-based switch fabrics will be addressed.