TAPES—Trace-based architecture performance evaluation with SystemC

Abstract

The design of today's System-on-Chip (SoC) architectures faces many challenges in respect to the involved complexity and heterogeneity. An early and systematic exploration of alternatives is mandatory to find a solution that meets all design requirements. Therefore, the experience of system architects has to be supplemented with efficient performance evaluation methods and tools that help in the broad exploration of the solution space. This article describes TAPES (Trace-based Architecture Performance Evaluation with SystemC), an approach that supports system designers in the performance evaluation of SoC architectures. The concept captures the functionality of the architecture in the form of traces for each resource. The trace primitives making up a trace are translated at simulation run-time into transactions and superposed on the system architecture. The method uses SystemC as modeling language, requires low modeling effort and yet provides accurate results within reasonable turnaround times. A concluding application example for the exploration of a network processor architecture demonstrates the effectiveness of the TAPES approach.