Network Processing Applications Research Articles

Real-time automatic integrated monitoring of barn environment and dairy cattle behaviour: Technical implementation and evaluation on three commercial farms

Due to increasing herd sizes and automation on dairy farms there is an important need for automated monitoring of cow production, health, and welfare. Despite much progress in automatic monitoring techniques, there is still a need to integrate data from multiple sources to create a comprehensive overview and accurate diagnosis of a cow’s state. To aid the technological development of data integration, a prototype of an open and customizable automatic system that integrates data from multiple sensors relating to barn environment and cow behaviour was developed. The system integrates data from sensors that measure barn climate (e.g., temperature, humidity, wind speed), air quality (e.g., CO2 concentration), water use and temperature, the moisture and temperature of the litter and cow behaviour (e.g., lying, eating, ruminating). An external weather system and video recording system are also included. The system’s architecture consists of four main elements: sensors, nodes, gateways, and backend. The data are recorded by sensors, then locally processed on custom-developed sensor nodes, and then transmitted via radio channels to local gateways that combine the data from multiple nodes and transmit them to distributed digital storage (“the cloud”) via a 3G/4G cellular network. On the cloud, the data are further processed and stored in a database. The data are then presented to the user continuously and in real time on a dashboard that can be accessed via the internet. In the design of the local wireless network, care was taken to avoid data packet collision and thus to minimize data loss. To test the system’s performance, the system was installed and operated on three commercial dairy cattle farms for one year. The system provided high data stability with minimal loss and outliers, showing that the system is reliable and suitable for long term application on commercial dairy farms. The system’s architecture, communication network, and data processing and visualization applications form an open framework for research and development purposes, allowing it to be customized and fine-tuned before being deployed as a management assistant on commercial dairy farms. Missing elements that should be added in the future are the integration of the data from the milking parlour and cow identification. Algorithms to integrate information from multiple sensors can be added to provide a comprehensive system that monitors all aspects related to cow welfare, health, and production automatically, remotely and in real time, thereby supporting farmers in important management decision-making.

A Hardware- and Accuracy-Efficient Approximate Multiplier with Error Compensation for Neural Network and Image Processing Applications

A Hardware- and Accuracy-Efficient Approximate Multiplier with Error Compensation for Neural Network and Image Processing Applications

Performance of Deep Learning Pickers in Routine Network Processing Applications

Abstract Picking arrival times of P and S phases is a fundamental and time-consuming task for the routine processing of seismic data acquired by permanent and temporary networks. A large number of automatic pickers have been developed, but to perform well they often require the tuning of multiple parameters to adapt them to each dataset. Despite the great advance in techniques, some problems remain, such as the difficulty to accurately pick S waves and earthquake recordings with a low signal-to-noise ratio. Recently, phase pickers based on deep learning (DL) have shown great potential for event identification and arrival-time picking. However, the general adoption of these methods for the routine processing of monitoring networks has been held back by factors such as the availability of well-documented software, computational resources, and a gap in knowledge of these methods. In this study, we evaluate recent available DL pickers for earthquake data, comparing the performance of several neural network architectures. We test the selected pickers using three datasets with different characteristics. We found that the analyzed DL pickers (generalized phase detection, PhaseNet, and EQTransformer) perform well in the three tested cases. They are very efficient at ignoring large-amplitude transient noise and at picking S waves, a task that is often difficult even for experienced analysts. Nevertheless, the performance of the analyzed DL pickers varies widely in terms of sensitivity and false discovery rate, with some pickers missing a significant percentage of true picks and others producing a large number of false positives. There are also variations in run time between DL pickers, with some of them requiring significant resources to process large datasets. In spite of these drawbacks, we show that DL pickers can be used efficiently to process large seismic datasets and obtain results comparable or better than current standard procedures.

Research on Data Release and Location Monitoring Technology of Sensor Network Based on Internet of Things

The Internet of Things is another information technology revolution and industrial wave after computer, Internet and mobile communication. It is becoming a key foundation and an important engine for the green, intelligent and sustainable development of economic society. The new networked intelligent production mode characterized by the integration innovation of the Internet of Things is shaping the core competitiveness of the future manufacturing industry. The application of sensor network data positioning and monitoring technology based on the Internet of Things in industry, power and other industries is a hot field for the development of the Internet of Things. Sensor network processing and industrial applications are becoming increasingly complex, and new features have appeared in the sensor network scale and infrastructure in these fields. Therefore, the Internet of Things perception data processing has become a research hotspot in the deep integration process between industry and the Internet of Things. This paper deeply analyzes and summarizes the characteristics of sensor network perception data under the new trend of the Internet of Things as well as the research on location monitoring technology, and makes in-depth exploration from the release and location monitoring of sensor network perception data of the Internet of Things. Sensor network technology integrated sensor technology, micro-electromechanical system technology, wireless communication technology, embedded computing technology and distributed information processing technology in one, with easy layout, easy control, low power consumption, flexible communication, low cost and other characteristics. Therefore, based on the release and location monitoring technologies of sensor network data based on the Internet of Things in different applications, this paper studies the corresponding networking technologies, energy management, data management and fusion methods. Standardization system in wireless sensor network low cost, and convenient data management needs, design the iot oriented middleware, and develops the software and hardware system, the application demonstration, the results show that the design of wireless sensor network based on iot data monitoring and positioning technology is better meet the application requirements, fine convenient integration of software and hardware, and standardized requirements and suitable for promotion.

Energy- and Quality-Efficient Approximate Multipliers for Neural Network and Image Processing Applications

Approximate computing is a new trend that trades off computational accuracy for lower energy dissipation and design complexity in various applications, where high precision is not a critical need. In this paper, energy- and quality- efficient approximate multipliers based on new approximate compressors are proposed. We use NAND gates for generating the complemented partial products, which reduces the number of transistors. Furthermore, new approximate compressors with different accuracy and performance characteristics are designed. Accordingly, three hybrid approximate multipliers offering different trade-offs between accuracy and hardware efficiency are proposed. The proposed designs are simulated using HSPICE with the 7nm FinFET model as a modern technology. Furthermore, the efficacies of the approximate multipliers in the neural network and image processing applications are evaluated using MATLAB. According to the results, the proposed designs provide far better compromises between the quality and energy metrics in comparison with the previous designs and can be considered as efficient alternatives for the exact multipliers in neural network and image processing applications.

Hadoop MapReduce Performance on SSDs for Analyzing Social Networks

Abstract The advent of Solid State Drives (SSDs) stimulated a lot of research to investigate and exploit to the extent possible the potentials of the new drive. The focus of this work is on the investigation of the relative performance and benefits of SSDs versus hard disk drives (HDDs) when they are used as underlying storage for Hadoop's MapReduce. In particular, we depart from all earlier relevant works in that we do not use their workloads, but examine MapReduce tasks and data suitable for performing analysis of complex networks which present different execution patterns. Despite the plethora of algorithms and implementations for complex network analysis, we carefully selected our “benchmarking methods” so that they include methods that perform both local and network-wide operations in a complex network, and also they are generic enough in the sense that they can be used as primitives for more sophisticated network processing applications. We evaluated the performance of SSDs and HDDs by executing these algorithms on real social network data and excluding the effects of network bandwidth which can severely bias the results. The obtained results confirmed in part earlier studies which showed that SSDs are beneficial to Hadoop. However, we also provided solid evidence that the processing pattern of the running application has a significant role, and thus future studies must not blindly add SSDs to Hadoop, but they should build components for assessing the type of processing pattern of the application and then direct the data to the appropriate storage medium.

Scalable Algorithms for NFA Multi-Striding and NFA-Based Deep Packet Inspection on GPUs

Finite state automata (FSA) are used by many network processing applications to match complex sets of regular expressions in network packets. In order to make FSA-based matching possible even at the ever-increasing speed of modern networks, multi-striding has been introduced. This technique increases input parallelism by transforming the classical FSA that consumes input byte by byte into an equivalent one that consumes input in larger units. However, the algorithms used today for this transformation are so complex that they often result unfeasible for large and complex rule sets. This paper presents a set of new algorithms that extend the applicability of multi-striding to complex rule sets. These algorithms can transform nondeterministic finite automata (NFA) into their multi-stride form with reduced memory and time requirements. Moreover, they exploit the massive parallelism of graphical processing units for NFA-based matching. The final result is a boost of the overall processing speed on typical regex-based packet processing applications, with a speedup of almost one order of magnitude compared to the current state-of-the-art algorithms.

Per-Flow Queue Management with Succinct Priority Indexing Structures for High Speed Packet Scheduling

Priority queues are essential building blocks for implementing advanced per-flow service disciplines and hierarchical quality-of-service at high-speed network links. Scalable priority queue implementation requires solutions to two fundamental problems. The first is to sort queue elements in real time at ever increasing line speeds (e.g., at OC-768 rates). The second is to store a huge number of packets (e.g., millions of packets). In this paper, we propose novel solutions by decomposing the problem into two parts, a succinct priority index (PI) in SRAM that can efficiently maintain a real-time sorting of priorities, coupled with a DRAM-based implementation of large packet buffers. In particular, we propose three related novel succinct PI data structures for implementing high-speed PIs: a PI, a counting priority index (CPI), and a pipelined counting priority index (pCPI). We show that all three structures can be very compactly implemented in SRAM using only ⊖(U) space, where U is the size of the universe required to implement the priority keys (time stamps). We also show that our proposed PI structures can be implemented very efficiently as well by leveraging hardware-optimized instructions that are readily available in modern 64-bit processors. The operations on the PI and CPI structures take ⊖(logW U) time complexity, where W is the processor word length (i.e., W = 64). Alternatively, operations on the pCPI structure take amortized constant time with only ⊖(logW U) pipeline stages (e.g., only four pipeline stages for U = 16 million). Finally, we show the application of our proposed PI structures for the scalable management of large packet buffers at line speeds. The pCPI structure can be implemented efficiently in high-performance network processing applications such as advanced per-flow scheduling with quality-of-service guarantee.

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

A multicore FPGA platform with cache-integrated network interfaces (NIs) has been developed, appropriate for scalable multicores, that combine the best of two worlds - the flexibility of caches (using implicit communication) and the efficiency of scratchpad memories (using explicit communication). Furthermore, the proposed scheme provides virtualized user-level RDAM capabilities and special hardware primitives (counter, queues) for the communication and synchronization of the cores. This paper presents how the proposed architecture can be utilized in the domain of network processing applications using the hardware synchronization mechanisms. Two representatives network processing benchmarks are used; one for header processing and one for payload processing. The Multiple Reader Queue (MRQ) scheme is utilized in the case of header processing, while in the case of payload processing where transfer of bulk data is required, the user-level RDMA scheme is utilized. These applications are mapped and evaluated to an FPGA platform with up to 24 processors. The performance evaluation in the domain of network processing shows that the proposed scheme can offer low latency communication and increased programming efficiency while it also offloads the processor from the communication and synchronization processes.

Robust Pipelined Memory System with Worst Case Performance Guarantee for Network Processing

Many network processing applications require wirespeed access to large data structures or a large amount of packet and flow-level data. Therefore, it is essential for the memory system of a router to be able to support both read and write accesses to such data at link speeds. As link speeds continue to increase, router designers are constantly grappling with the unfortunate trade-offs between the speed and cost of SRAM and DRAM. The capacity of SRAMs is woefully inadequate in many cases and it proves too costly to store large data structures entirely in SRAM, while DRAM is viewed as too slow for providing wirespeed updates at such high speed. In this paper, we analyze a robust pipelined memory architecture that can emulate an ideal SRAM by guaranteeing with very high probability that the output sequence produced by the pipelined memory architecture is the same as the one produced by an ideal SRAM under the same sequence of memory read and write operations, except time shifted by a fixed pipeline delay of \Delta. Given a fixed pipeline delay abstraction, no interrupt mechanism is required to indicate when read data are ready or a write operation has completed, which greatly simplifies the use of the proposed solution. The design is based on the interleaving of DRAM banks together with the use of a reservation table that serves in part as a data cache. In contrast to prior interleaved memory solutions, our design is robust under all memory access patterns, including adversarial ones, which we demonstrate through a rigorous worst case theoretical analysis using a combination of convex ordering and large deviation theory.

Design and Implementation of NIDS String Matching Based on SOPC

String matching is a key problem in many network processing applications. Current implementations of this process using software are time consuming. This paper presents a string matching system that based on FPGA. This paper uses DM9000A to receive network data and uses Snort rule and HashMem function to match pattern. With software simulation the conflict pattern of Snort rules found out and processed separately. In the system, conflict can be high-speed solved. With the PC handle string matching that more than 16 Byte, the FPGA processing speed has improved greatly .The experimental results show that the system throughput is 1.22Gbps, more than 20 times of the software method. When processing more Snort rules system throughput is not affected. Experimental results show that the system can quickly adapt to the demand for hardware reconfiguration and meet the network application requirements.

Analysis of network processing workloads

Network processing is becoming an increasingly important paradigm as the Internet moves towards an architecture with more complex functionality in the data path. Modern routers not only forward packets, but also process headers and payloads to implement a variety of functions related to security, performance, and customization. It is important to get a detailed understanding of the workloads associated with this processing in order to be able to develop efficient network processing engines. We present a tool called PacketBench, which provides a framework for implementing network processing applications and obtaining an extensive set of workload characteristics. For statistics collection, PacketBench provides the ability to derive a number of microarchitectural and networking related metrics. We show a range of workload results that focus on individual packets and the variation between them. The understanding of workload details of network processing has many practical applications. We discuss how PacketBench results can be used to estimate network processing delay that are very close to those obtained from measurement.

Adaptive Bloom Filter: A Space-Efficient Counting Algorithm for Unpredictable Network Traffic

The Bloom Filter (BF), a space-and-time-efficient hash-coding method, is used as one of the fundamental modules in several network processing algorithms and applications such as route lookups, cache hits, packet classification, per-flow state management or network monitoring. BF is a simple space-efficient randomized data structure used to represent a data set in order to support membership queries. However, BF generates false positives, and cannot count the number of distinct elements. A counting Bloom Filter (CBF) can count the number of distinct elements, but CBF needs more space than BF. We propose an alternative data structure of CBF, and we called this structure an Adaptive Bloom Filter (ABF). Although ABF uses the same-sized bit-vector used in BF, the number of hash functions employed by ABF is dynamically changed to record the number of appearances of a each key element. Considering the hash collisions, the multiplicity of a each key element on ABF can be estimated from the number of hash functions used to decode the membership of the each key element. Although ABF can realize the same functionality as CBF, ABF requires the same memory size as BF. We describe the construction of ABF and IABF (Improved ABF), and provide a mathematical analysis and simulation using Zipf's distribution. Finally, we show that ABF can be used for an unpredictable data set such as real network traffic.

FPGA based string matching for network processing applications

String matching is a key problem in many network processing applications. Current implementations of this process using software are time consuming and cannot meet gigabit bandwidth requirements. Implementing this process in hardware improves the search time considerably and has several other advantages. This paper presents an array based hardware implementation of this time consuming process for network intrusion detection and directory lookup applications using reconfigurable hardware. These designs are coded in VHDL targeting a Xilinx Virtex-II Pro FPGA and are evaluated in terms of the speed and resource utilization.

ILP and heuristic techniques for system-level design on network processor architectures

Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.

Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications

This paper presents results of a simulated performance evaluation of RISC-based SoC platforms for networking applications and compares them to measurement results on an FPGA prototype. We use our SystemC simulation environment, which is calibrated with a reference implementation. Starting with an analysis of the reference scenario, two approaches for improvements are investigated: at first, hardware assists are added, which offload the CPU from compute-intensive bit-level manipulations. Secondly, the concept of flexible processing paths as proposed in FlexPath NP with AutoRoute is evaluated, in which certain parts of the traffic can bypass the central CPU cluster. For each of the three scenarios we determine the maximum throughput and discuss the improvements and limitations of each solution. It can be shown that a FlexPath NP may achieve up to 2.5 times the throughput of the reference scenario. Simulation results are compared to additional measurements on the FPGA platform, which led to a further refinement of our system model. The investigations provide a deeper insight on the practical benefits and limitations of system-level performance simulations.

FEADS: A Framework for Exploring the Application Design Space on Network Processors

Network processors are designed to handle the inherently parallel nature of network processing applications. However, partitioning and scheduling of application tasks and data allocation to reduce memory contention remain as major challenges in realizing the full performance potential of a given network processor. The large variety of processor architectures in use and the increasing complexity of network applications further aggravate the problem. This work proposes a novel framework, called FEADS, for automating the task of application partitioning and scheduling for network processors. FEADS uses the simulated annealing approach to perform design space exploration of application mapping onto processor resources. Further, it uses cyclic and r-periodic scheduling to achieve higher throughput schedules. To evaluate dynamic performance metrics such as throughput and resource utilization under realistic workloads, FEADS automatically generates a Petri net (PN) which models the application, architectural resources, mapping and the constructed schedule and their interaction. The throughput obtained by schedules constructed by FEADS is comparable to that obtained by manual scheduling for linear task flow graphs; for more complicated task graphs, FEADS' schedules have a throughput which is upto 2.5 times higher compared to the manual schedules. Further, static scheduling of tasks results in an increase in throughput by upto 30% compared to an implementation of the same mapping without task scheduling.

Fast hash table lookup using extended bloom filter

Hash tables are fundamental components of several network processing algorithms and applications, including route lookup, packet classification, per-flow state management and network monitoring. These applications, which typically occur in the data-path of high-speed routers, must process and forward packets with little or no buffer, making it important to maintain wire-speed throughout. A poorly designed hash table can critically affect the worst-case throughput of an application, since the number of memory accesses required for each lookup can vary. Hence, high throughput applications require hash tables with more predictable worst-case lookup performance. While published papers often assume that hash table lookups take constant time, there is significant variation in the number of items that must be accessed in a typical hash table search, leading to search times that vary by a factor of four or more.We present a novel hash table data structure and lookup algorithm which improves the performance over a naive hash table by reducing the number of memory accesses needed for the most time-consuming lookups. This allows designers to achieve higher lookup performance for a given memory bandwidth, without requiring large amounts of buffering in front of the lookup engine. Our algorithm extends the multiple-hashing Bloom Filter data structure to support exact matches and exploits recent advances in embedded memory technology. Through a combination of analysis and simulations we show that our algorithm is significantly faster than a naive hash table using the same amount of memory, hence it can support better throughput for router applications that use hash tables.

Experimental parallel implementation of a wavelet-based still image encoder

A still image encoder implementation is presented for a multi-DSP system called PARNEU, which has previously been developed for neural network and signal processing applications. The core of the implementation is based on experimental mappings of discrete wavelet transform (DWT) on the parallel processor architecture. PARNEU has a flexible interconnection network architecture with message passing, which allows adding more processing units (PUs) to the system whenever more computational power is needed. Program code can be written to adapt to the number of PUs. This is utilized in the presented encoder implementation with emphasis on load balancing among processors as well as on balance between communication and computation. Performance of the implementation is measured with a scaleable number of processors and compared to a sequential reference implementation. Results show that the DWT phase can be efficiently parallelized on PARNEU with 95.6% of its time spent on true parallel computation. The overall speedup with four processors is 2.25, which could be improved by further optimization of an adaptive scanning phase of the encoder.

On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications

Instruction Reuse is a microarchitectural technique that exploits dynamic instruction repetition to remove redundant computations at run-time. In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications and attempt to answer the following questions: (1) How much of instruction repetition can be reused in packet processing applications?, (2) Can the temporal locality of network traffic be exploited to reduce interference in the Reuse Buffer and improve reuse? and (3) What is the effect of reuse on microarchitectural features such as resource contention and memory accesses? We use an execution driven simulation methodology to evaluate instruction reuse and find that for the benchmarks considered, 1 to 50% of the dynamic instructions are reused yielding performance improvement between 1 and 20%. To further improve reuse, a flow aggregation scheme as well as an architecture for exploiting the same is proposed. This scheme is mostly applicable to header processing applications and exploits temporal locality in packet data to uncover higher reuse. As a side effect, instruction reuse reduces memory traffic and improves performance.