Routing Algorithm For Network-on-Chip Research Articles

DeepNR: An adaptive deep reinforcement learning based NoC routing algorithm

Network-on-Chip (NoC) has become a cost-effective communication interconnect for Tiled Chip Multicore Processor systems. The communication between cores is done through packet exchange. As the computational intensity of applications increases, the amount of packet exchange between cores will also increase. The improper routing of these packets will result in high congestion thereby degrading the system performance. This marks the need for congestion-aware routing in NoC. In the real world, the applications running in NoC create diverse traffic, which in turn creates challenges in routing. Such challenges have resulted in more researchers relying on machine learning algorithms to tackle them. However, the issues pertaining to storage overhead and packet latency prevail in such methodologies. This paper presents an adaptive routing algorithm DeepNR, which uses a deep reinforcement learning approach. The proposed approach considers network information for state representation, routing directions for actions, and queuing delay for reward function. Experiments carried out on synthetic as well as real-time traffics to demonstrate the effectiveness and efficiency of DeepNR using the Gem5 simulator. The results obtained for DeepNR indicate a reduction of up to 21.25% and 44% in overall packet latency under high traffic conditions on real and synthetic traffic respectively, as compared to the existing approaches. Also, DeepNR achieves a throughput of above 90% in both the traffic scenarios.

A Path-Wise Scheme for Simpler Mesh-of-Tree Model in Network-on-Chip Designs

Abstract The needs of the chip are growing on a daily basis as extremely large size integrated circuits evolve fast. As a result, the network-on-chip (NoC) was suggested and successfully developed to address the issue of communication on-chip. Current research focuses on NoC topology and routing algorithms that have a substantial influence on network performance. Because low power is a priority, the Mesh-of-Tree (MoT) architecture is preferable. However, certain MoT routers may perform extensive communication activities, which means they consume more power and are more likely to become hotspots. To improve power consumption, we presented a Simpler Mesh-of-Tree (SMoT) architecture based on MoT in this study. We also suggested a path-wise routing scheme for the Internet of Things, which takes into account both network traffic and the shortest path between two points. By altering the direction of data forwarding to reduce network latency, our methodology spreads communication over the whole network. When compared to MoT, our suggested strategy can lower network power consumption by 5.39%–23.3% while also reducing network latency by 4.23%–27.28%.

HAFTA: Highly adaptive fault‐tolerant routing algorithm for two‐dimensional network‐on‐chips

AbstractLearning‐based routing algorithms are good candidates for two‐dimensional Network‐on‐Chip (NoC) architectures since they can give good path selection decisions by combining current and past state of the network traffic. On the other hand, they generally send packets through nonminimal paths in order to detour congested areas in an attempt to minimize the communication cost. Since adapting to the traffic changes takes time to gather enough feedback information by the applied learning model, non‐minimal paths may take more time than the congested minimal paths. In this work, we incorporate a probabilistic method to a Q‐learning‐based NoC routing algorithm for selecting a minimal or nonminimal path to minimize the negative effect of learning duration. We also consider the errors in the architecture and propose a fault‐tolerance mechanism that detects both transient and permanent link errors. We compared our method against a standard Q‐learning‐based routing algorithm on several traffic models in terms of throughput and latency. The results show that our method outperforms its counterpart up to 30% in latency and 7% in throughput.

A survey of routing algorithm for mesh Network-on-Chip

With the rapid development of semiconductor industry, the number of cores integrated on chip increases quickly, which brings tough challenges such as bandwidth, scalability and power into on-chip interconnection. Under such background, Network-on-Chip (NoC) is proposed and gradually replacing the traditional on-chip interconnections such as sharing bus and crossbar. For the convenience of physical layout, mesh is the most used topology in NoC design. Routing algorithm, which decides the paths of packets, has significant impact on the latency and throughput of network. Thus routing algorithm plays a vital role in a wellperformed network. This study mainly focuses on the routing algorithms of mesh NoC. By whether taking network information into consideration in routing decision, routing algorithms of NoC can be roughly classified into oblivious routing and adaptive routing. Oblivious routing costs less without adaptiveness while adaptive routing is on the contrary. To combine the advantages of oblivious and adaptive routing algorithm, half-adaptive algorithms were proposed. In this paper, the concepts, taxonomy and features of routing algorithms of NoC are introduced. Then the importance of routing algorithms in mesh NoC is highlighted, and representative routing algorithms with respective features are reviewed and summarized. Finally, we try to shed light upon the future work of NoC routing algorithms.

A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures

In this paper, we propose SVR-NoC, a network-on-chip (NoC) latency model using support vector regression (SVR). More specifically, based on the application communication information and the NoC routing algorithm, the channel and source queue waiting times are first estimated using an analytical queuing model with two equivalent queues. To improve the prediction accuracy, the queuing theory-based delay estimations are included as features in the learning process. We then propose a learning framework that relies on SVR to collect training data and predict the traffic flow latency. The proposed learning methods can be used to analyze various traffic scenarios for the target NoC platform. Experimental results on both synthetic and real-application traffic demonstrate on average less than 12% prediction error in network saturation load, as well as more than 100× speedup compared to cycle-accurate simulations can be achieved.

Master-based routing algorithm and communication-based cluster topology for 2D NoC

As size of chip is becoming smaller with growth in technology, and due to increase in number of cores, system-on-chip (SoC) becomes very complex. Network-on-chip (NoC) provides best solution to SoC by reducing communication overhead. The basic concern of NoC is the speed, performance and accuracy along with the small size of chip. The existing NoC topologies such as mesh topology, bus topology, torus topology, fat tree topology does not provide optimized performance. In this paper, we have proposed communication-based cluster topology (CBCT), which is based on 2H, i.e., heterogeneous and hybrid, proves to be more efficient topology by providing better performance due to reduction in latency, link utilization and energy consumption involved during communication. In experimental result, CBCT approach is compared with 2D mesh topology and CBCT proves to provide better results in terms of an end-to-end latency, network latency, packet latency, sink bandwidth, loss probability, link utilization and energy consumption of a topology.

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

In this paper, an efficient application mapping approach is proposed for the co-optimization of reliability, communication energy, and performance (CoREP) in network-on-chip (NoC)-based reconfigurable architectures. A cost model for the CoREP is developed to evaluate the overall cost of a mapping. In this model, communication energy and latency (as a measure of performance) are first considered in energy latency product (ELP), and then ELP is co-optimized with reliability by a weight parameter that defines the optimization priority. Both transient and intermittent errors in NoC are modeled in CoREP. Based on CoREP, a mapping approach, referred to as priority and ratio oriented branch and bound (PRBB), is proposed to derive the best mapping by enumerating all the candidate mappings organized in a search tree. Two techniques, branch node priority recognition and partial cost ratio utilization, are adopted to improve the search efficiency. Experimental results show that the proposed approach achieves significant improvements in reliability, energy, and performance. Compared with the state-of-the-art methods in the same scope, the proposed approach has the following distinctive advantages: 1) CoREP is highly flexible to address various NoC topologies and routing algorithms while others are limited to some specific topologies and/or routing algorithms; 2) general quantitative evaluation for reliability, energy, and performance are made, respectively, before being integrated into unified cost model in general context while other similar models only touch upon two of them; and 3) CoREP-based PRBB attains a competitive processing speed, which is faster than other mapping approaches.

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints

The flexibility of manycore systems to extensive applications is achieved by reconfiguring the interconnections between processing elements (PEs) and the function of PEs. The efficiency of the system is crucially determined by the mapping technique of applications. In this paper, a highly flexible reliability-aware application mapping approach is proposed for manycore network-on-chip (NoC) systems. A reliability cost model (RCM) is first presented to measure the reliability cost for a mapping pattern. This model uses the binary number 0/1 to model the reliability cost of each communication path. The overall reliability cost of a mapping pattern is evaluated by taking the cost of each path as a discrete random variable. Based on RCM, a mapping method called reliability cost ratio based branch and bound (RCRBB) is used. With this method, the best mapping among all the possible patterns is found efficiently by discarding those nonoptimal candidate mappings at early stages. The proposed application mapping approach with reliability awareness is applicable to various NoC topologies and routing algorithms, while other state-of-the-art approaches on the same topic are only limited to a specific topology and routing algorithm. Even for the same NoC architecture, the proposed approach shows significant superiority in many aspects. Experiments show that RCRBB achieves up to 9.07% reliability enhancement on average. Also, it outperforms other approaches in throughput and latency with a relatively low run time.

Design of Router Supporting Multiply Routing Algorithm for NoC

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

Acyclic LBDRe: fault-tolerant routing algorithm for network on chip

In this paper, as technology scales higher, reliability of network on chip (NoC) becomes key issue. It decreases the transistor reliability by connecting the increasing number of on-chip resources. Consequently, this paper presents an efficient fault tolerant routing algorithm for the NoC architecture. We propose acyclic LBDRe which is based on extended logic-based distributed routing (LBDRe) array. Minimal set of turns are prohibited to avoid deadlock. The algorithm guarantees that not more than 1/3 of all turns in the NoC architecture become prohibited. The proposed routing algorithm outperforms substantially the existing fault tolerant routing algorithms. Simulation results show that the proposed method can noticeably reduce the overall average latency and total network power with minimum hardware cost for the fault tolerant routing algorithm for NoC.

Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip

Problem statement: Network on Chip (NoC) is an appropriate candidate to implement interconnections in SoCs. Increase in number of IP blocks in 2D NoC will lead to increase in chip area, global interconnect, length of the communication channel, number of hops transversed by a packet, latency and difficulty in clock distribution. 3D NoC is evolved to overcome the drawbacks of 2D NoC. Topology, switching mechanism and routing algorithm are major area of 3D NoC research. In this study, three topologies (3D-MT, 3D-ST and 3D-RNT) and routing algorithm for 3D NoC are presented. Approach: Experiment is conducted to evaluate the performance of the topologies and routing algorithm. Evaluation parameters are latency, probability and network diameter and energy dissipation. Results: It is demonstrated by a comparison of experimental results analysis that 3D-RNT is a suitable candidate for 3D NoC topology. Conclusion: The performance of the topologies and routing algorithm for 3D NoC is analysed. 3D-MT is not a suitable candidate for 3D NoC, 3D-ST is a suitable candidate provided interlayer communications are frequent and 3D-RNT is a suitable candidate as interlayer communications are limited.