Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints

Abstract

The flexibility of manycore systems to extensive applications is achieved by reconfiguring the interconnections between processing elements (PEs) and the function of PEs. The efficiency of the system is crucially determined by the mapping technique of applications. In this paper, a highly flexible reliability-aware application mapping approach is proposed for manycore network-on-chip (NoC) systems. A reliability cost model (RCM) is first presented to measure the reliability cost for a mapping pattern. This model uses the binary number 0/1 to model the reliability cost of each communication path. The overall reliability cost of a mapping pattern is evaluated by taking the cost of each path as a discrete random variable. Based on RCM, a mapping method called reliability cost ratio based branch and bound (RCRBB) is used. With this method, the best mapping among all the possible patterns is found efficiently by discarding those nonoptimal candidate mappings at early stages. The proposed application mapping approach with reliability awareness is applicable to various NoC topologies and routing algorithms, while other state-of-the-art approaches on the same topic are only limited to a specific topology and routing algorithm. Even for the same NoC architecture, the proposed approach shows significant superiority in many aspects. Experiments show that RCRBB achieves up to 9.07% reliability enhancement on average. Also, it outperforms other approaches in throughput and latency with a relatively low run time.