Network-on-Chip Research Articles

A sampling-based acceleration method for heterogeneous chiplet NoC simulations

To tackle the challenges posed by Moore’s Law, Chiplet technology emerges as a promising solution. Chiplets comprising CPUs and accelerators are connected by Networks-on-Chip (NoC) for large-scale integration and efficient communications. However, the slow simulation speed of NoCs has become a bottleneck, limiting the overall performance of chiplet simulations. Existing solutions only focus on accelerating NoC simulation in homogeneous architecture. In this paper, we introduce a novel TOPSIS-based Heterogeneous Trace Score-sampling method (THTS) for faster NoC simulation in heterogeneous architecture. THTS enables quick and accurate sampling of representative NoC traces. Additionally, we propose a weight exploration model to further enhance sampling accuracy. Compared with the traditional NoC sampling method (NoCLabs), THTS reduces the error of the average packet latency by 22.17% and the total simulation time by 1.6 folds. THTS estimates the NoC performance with an average loss less than 5%, while speeding up the NoC simulation by up to 3 times. In addition, under different weight space sizes, the time required for the weight exploration model to solve the optimal weight vector is within seconds, remarkably speeding up the solution process. Notably, the predicted NoC simulation error under the optimal weight is only 1.42%.

A High Scalability Memory NoC with Shared-Inside Hierarchical-Groupings for Triplet-Based Many-Core Architecture

Innovative processor architecture designs are shifting towards Many-Core Architectures (MCAs) to meet the future demands of high-performance computing as the limits of Moore’s Law have almost been reached. Many-core processors utilize shared memory hierarchies to achieve high-speed memory systems, improving memory access efficiency. However, as the number of cores multiplies, the scalability of this system is significantly constrained by the increased proportion of long-distance and Non-Uniform Memory Access (NUMA). Improving the scalability of MCAs is crucial for achieving large/super-scale general-purpose many-core processors. This work proposes a high scalability memory Network-on-Chip (NoC) for Triplet-Based Many-Core Architecture (TriBA), named TriBA-mNoC. TriBA-mNoC maintains a consistent core-to-core spacing as the network scale increases, effectively preventing increased long-distance memory access latency. Moreover, it leverages an inherent advantage of shared-inside hierarchical-groupings, alleviating common NUMA issues in the NoC design. Evaluations of static network characteristics show that TriBA-mNoC outperforms most classical NoCs in network diameter, average distance, and cost. TriBA-mNoC can be integrated with TriBA in the same silicon die with a tile-like floorplan, forming a novel NoC called TriBA-NoC, which can combine the strengths of both networks to maximize the architecture performance. We evaluated the memory access performance and scalability of TriBA-NoC using the mathematical evaluation models and actual simulations with real traffic (PARSEC 3.0 and SPLASH-2) at different network scales. The mathematical evaluation results indicate that TriBA-NoC achieves an aggregate speedup of approximately 3x compared with 2D-Mesh for a similar number of cores. Furthermore, TriBA-NoC’s single-core speedup efficiency remains stable as the number of cores increases under the same cache hit ratio, while 2D-Mesh experiences a rapid decline, highlighting TriBA-NoC’s exceptional scalability. Finally, the actual traffic simulation results show that TriBA-NoC achieves an average memory access latency and time reduction of 25.90% − 40.50% and 5.61% − 31.69% respectively, compared with 2D-Mesh.

Buffer Association of Network on Chip (NoC) Using Simulated Network

Buffer Association of Network on Chip (NoC) Using Simulated Network

On-chip human lymph node stromal network for evaluating dendritic cell and T-cell trafficking

The lymph node paracortex, also known as the T-cell zone, consists of a network of fibroblastic reticular cells (FRCs) that secrete chemokines to induce T-cell and dendritic cell (DC) trafficking into the paracortex. To model the lymph node paracortex, we utilize multi-channel microfluidic devices to engineer a 3D lymph node stromal network from human cultured FRCs embedded in a collagen I-fibrin hydrogel. In the hydrogel, the FRCs self-assemble into an interconnected network, secrete the extracellular matrix proteins entactin, collagen IV, and fibronectin, as well as express an array of immune cell trafficking chemokines. Although the engineered FRC network did not secrete characteristic CCR7-ligand chemokines (i.e. CCL19 and CCL21), human primary TNF-αmatured monocyte-derived DCs, CD45RA+T-cells, and CD45RA-T-cells migrate toward the lymph node stromal network to a greater extent than toward a blank hydrogel. Furthermore, the FRCs co-recruit DCs and antigen-specific T-cells into the lymph node stromal network. This engineered lymph node stromal network may help evaluate how human DCs and T-cells migrate into the lymph node paracortex via CCR7-independent mechanisms.

Network-on-Chip (NoC) Applications for IoT-Enabled Chip Systems: Latest Designs and Modern Applications

Network-on-Chip (NoC) technology has emerged as a critical innovation in the field of integrated circuit design, addressing the growing demands for efficient, scalable, and high-performance on-chip communication. This review provides a comprehensive examination of NoC, highlighting its architecture, key features, and current applications. NoC leverages a network-based approach, utilizing routers and links to interconnect various components on a chip, thereby overcoming the limitations of traditional System-on-chip (SoC) architectures that rely on shared bus systems. The review underscores NoC’s superior communication efficiency, scalability, and reduced latency, which are essential for modern high-performance computing, multi-core processors, and advanced embedded systems. It also explores NoC’s ability to optimize power consumption through dynamic voltage scaling and power gating, making it a favorable choice for energy-efficient designs. Despite its complexity, NoC’s modularity and adaptability make it suitable for a wide range of applications, from artificial intelligence accelerators to high-performance data centers. In conclusion, NoC stands as a transformative technology that enhances the performance and scalability of integrated circuits, paving the way for more sophisticated and powerful electronic systems. As the demand for higher computational capabilities and efficiency continues to rise, NoC is poised to play an increasingly vital role in the advancement of electronic design and architecture.

A high-level simulator for Network-on-Chip

This study presents a high-level simulator for Network-on-Chip (NoC), designed for many-core architectures, and integrated with the PlatEMO platform. The motivation for developing this tool arose from the need to evaluate the behavior of application mapping algorithms and the routing, both aspects are essential in the implementation and design of NoC architectures. This analysis underscored the importance of having effective NoC simulators as tools that allow for studying and comparing various network technologies while ensuring a controlled simulation environment. During this investigation and evaluation, some simulators, such as Noxim, NoCTweak, and NoCmap, among others, offered configurable parameters for application traffic, options to synthetically define topology and packet traffic patterns. Additionally, they include mapping options that optimize latency and energy consumption, routing algorithms, technological settings such as the CMOS process, and measurement options for evaluating performance metrics such as throughput and power usage. However, while these simulators meet detailed technical demands, they are mostly restricted to analyzing the low-level elements of the architecture, thus hindering quick and easy under- standing for non-specialists. This insight underscored the challenge in developing a tool that balances detailed analysis with a comprehensive learning perspective, considering the specific restrictions of each simulator analyzed. Experiments demonstrated the proposed simulator efficacy in handling algorithms like GA, PSO, and SA variant, and, surprisingly, revealed limitations of the XY algorithm in Mesh topologies, indicating the need for further investigation to confirm these findings. Future work will expand the simulator functionalities, incorporating a broader range of algorithms and performance metrics, to establish it as an indispensable tool for research and development in NoCs.

Low-power coding method in data transmission systems

The object of the study is the Network-on-Chip (NoC) technology, which has become a popular choice for the on-chip communication architecture of modern System-on-Chip (SoC) devices. The subject matter of the article is methods of reducing dissipated power in NoC and SoC. The goal of the work is: development of a low-power coding method that allows for the efficient transmission or storage of information. The following tasks are solved in the article: analysis of classification methods for combinatorial structures, construction a system of typical representatives and analysis of their characteristics. The research methods are based on the use of set theory, system theory and combinatorics. The following results are obtained: analyzed factors that affect the dissipated power, considered principles of constructing energy-efficient codes. It is shown that switching activity significantly affects the total power and one of the effective methods for reducing switching activity during communication between devices or on-chip communication is the use of low-power coding methods. A method of hierarchical classification of unit distance codes and algorithms for solving step-by-step problems have been developed. The method is based on the invariant approach and construction of a system of different representatives. Estimates of their number have been obtained, characteristics have been determined, and catalogs of typical representatives have been formed. Conclusions. The article analyzes factors that affect dissipated power, and considers the principles of constructing energy-efficient codes. A method of hierarchical classification of single distance codes and algorithms for solving step-by-step problems have been developed, and catalogs of typical representatives have been formed. The application of the developed method will allow developers to analyze and select codes with the best properties and, as a result, obtain better results in terms of network delays, energy costs, and other design limitations for computer systems.

Test scheduling of network-on-chip using hybrid WOA-GWO algorithm

The promising Network-on-Chip (NoC) model replaces the existing system-on-chip (SoC) model for complex VLSI circuits. Testing the embedded cores using NoC incurs additional costs in these SoC models. NoC models consist of network interface controllers, Internet Protocol (IP) data centers, routers, and network connections. Technological advancements enable the production of more complex chips, but longer testing times pose a potential problem. NoC packet switching networks provide high-performance interconnection, a significant benefit for IP cores. A multi-objective approach is created by integrating the benefits of the Whale Optimization Algorithm (WOA) and Grey Wolf Optimization (GWO). In order to minimize the duration of testing, the approach implements optimization algorithms that are predicated on the behavior of grey wolves and whales. The P22810 and D695 benchmark circuits are under consideration. We compare the test time with existing optimization techniques. We assess the effectiveness of the suggested hybrid WOA-GWO algorithm using fourteen established benchmark functions and an NP-hard problem. This proposed method minimizes the time needed to test the P22810 benchmark circuit by 69%, 46%, 60%, 19%, and 21% compared to the Modified Ant Colony Optimization, Modified Artificial Bee Colony, WOA, and GWO algorithms. In the same vein, the proposed method reduces the testing time for the d695 benchmark circuit by 72%, 49%, 63%, 21%, and 25% in comparison to the same algorithms. We experimented to determine the time savings achieved by adhering to the suggested procedure throughout the testing process.

Fault-tolerant routing for reliable packet transmission in on-chip networks

In deep submicron technology, integrated circuits are susceptible to various factors, leading to increased probabilities of chip failures. The routers within NoC, connecting processor cores, also experience elevated fault rates, thereby impacting normal communication between processors. Therefore, implementing fault-tolerant mechanisms in on-chip networks becomes particularly crucial. In this paper, we propose a fault-tolerant routing scheme to ensure the accurate transmission, injection, and ejection of packets, even in the event of router failures at any node in the NoC. We have enhanced the router architecture by integrating bypass controllers (BCs) to connect east–west and north–south links, and linking these BCs to the local. This modification enables uninterrupted communication between cores. Based on this architecture, we propose a straightforward routing algorithm aimed at minimizing detours and ensuring packet transmission along the shortest path , thus reducing transmission latency. Experimental results demonstrate that our proposed fault-tolerant scheme significantly enhances reliability under scenarios involving multiple faulty routers when compared to existing schemes.

F-Bypass: a low-power network-on-chip design utilizing bypass to improve network connectivity

With the development of transistor feature size to nanometer level, static power consumption has gradually become the main factor affecting the overall power consumption of network on chip (NoC). Power gating is an effective technology to reduce static power consumption, but it also brings new challenges, such as BET violation, wake-up latency and network connectivity. Therefore, a power gating method is needed to improve NoC performance and reduce static power consumption. This paper proposes a low-power bypass method, namely Forwarding bypass (F-Bypass). First, F-Bypass adds bypass paths between all input and output ports and the network interface (NI), and connects the pop-up port and injection port in NI through the bypass path. When the router is powered off, F-Bypass performs wake-up-free packet transmission, which reduces the break-even time (BET) violation and cumulative wake-up latency while ensuring network connectivity. Secondly, This paper add the modified VC state table to NI, so that the power-off router can perform normal traffic control. Finally, a new wake-up criterion is proposed, which can effectively avoid the frequent wake-up of power-off routers, and the detailed hardware implementation of F-Bypass is provided.The simulation results under integrated traffic load show that compared with the traditional scheme, the delay of F-Bypass is reduced by 2.2%, the throughput is increased by 13.1%, and the total static power consumption is reduced by 75.2%. Key performance indicators are superior to other solutions, and the increased area cost is moderate.

On-chip photoelectric hybrid convolutional accelerator based on Bragg grating array

We propose an on-chip photoelectric hybrid convolution accelerator based on Bragg grating array. The weight of the convolution kernel can be adjusted by controlling the central wavelengths of the Bragg grating array. We conducted simulation verification of the functionality and scalability of this on-chip photoelectric hybrid convolution accelerator. Subsequently, we constructed a neural network model to conduct handwritten digit classification simulations using this accelerator, achieving a simulation accuracy of 93.99%. Finally, the concept of the proposed on-chip photoelectric hybrid convolution accelerator is successfully verified. Due to the merits of Bragg grating, the proposed scheme paves the way for realizing high-performance on-chip optical neural networks.

Wireless sensor networks protocols, applications, and network-on-chip communications

A wireless sensor network (WSN) is a network consisting of self-governing sensors that are deployed in space and communicate with each other using wireless technology to monitor physical or environmental variables. These networks generally include compact, inexpensive sensor nodes equipped with sensing, processing, and communication functionalities. WSNs are specifically engineered to gather data from their immediate environment, do local data processing, and subsequently communicate pertinent information either to a central hub or to other interconnected nodes within the network. Continuous research in the domain of WSNs is devoted to advancing security concerns, developing novel sensing technologies, and optimizing communication protocols. The advancements in these domains enhance the ongoing development and efficiency of WSNs. The WSNs are very important for getting information from the real world in many situations. WSNs are flexible tools for keeping an eye on and controlling different environments because they have sensor nodes, wireless communication, and distributed processing. WSNs use network-on-chip (NoC) communication architecture to connect sensor nodes. The article explains the introduction to WSN, the background of wireless communication, motivation, ZigBee protocol, and WSN applications.

Proactive deadlock prevention based on traffic classification sub-graphs for triplet-based NoC TriBA-cNoC

Network topology and routing algorithms stand as pivotal decision points that profoundly impact the performance of Network-on-Chip (NoC) systems. As core counts rise, so does the inherent competition for shared resources, spotlighting the critical need for meticulously designed routing algorithms that circumvent deadlocks to ensure optimal network efficiency. This research capitalizes on the Triplet-Base Architecture (TriBA) and its Distributed Minimal Routing Algorithm (DM4T) to overcome the limitations of previous approaches. While DM4T exhibits performance advantages over previous routing algorithms, its deterministic nature and potential for circular dependencies during routing can lead to deadlocks and congestion. Therefore, this work addresses these vulnerabilities while leveraging the performance benefits of TriBA and DM4T. This work introduces a novel approach that merges a proactive deadlock prevention mechanism with Intermediate Adjacent Shortest Path Routing (IASPR). This combination guarantees both deadlock-free and livelock-free routing, ensuring reliable communication within the network. The key to this integration lies in a flow model-based data transfer categorization technique. This technique prevents the formation of circular dependencies. Additionally, it reduces redundant distance calculations during the routing process. By addressing these challenges, the proposed approach achieves improvements in both routing latency and throughput. To rigorously assess the performance of TriBA network topologies under varying configurations, extensive simulations were undertaken. The investigation encompassed both TriBA networks comprising 9 nodes and those with 27 nodes, employing DM4T, IASPR routing algorithms, and the proactive deadlock prevention method. The gem5 simulator, operating under the Garnet 3.0 network model using a standalone protocol for synthetic traffic patterns, was utilized for simulations at high injection rates, spanning diverse synthetic traffic patterns and PARSEC benchmark suite applications. Simulations rigorously quantified the effectiveness of the proposed approach, revealing reductions in average latency 40.17% and 34.05% compared to the lookup table and DM4T, respectively. Additionally, there were notable increases in average throughput of 7.48% and 5.66%.

Unidirectional and hierarchical on-chip interconnected architecture for large-scale hardware spiking neural networks

Spiking Neural Networks (SNNs) exhibit the strong capability to address spatiotemporal dynamic problems. Recent research has explored the hardware SNN systems to solve the spatiotemporal problems in real-time. The Network-on-Chip (NoC) is an effective scheme for building large-scale hardware SNNs. However, for the existing NoC-based hardware SNNs, large area overhead and hardware power are consumed by their interconnections, because of complex topologies and router structures. Therefore, in this work a novel Unidirectional and Hierarchical on-Chip Interconnected Architecture (UHCIA) is proposed to address this problem. The proposed UHCIA mainly combines the novel hybrid topology of unidirectional multiple loops and rings, and uses a deflection router technique. Experimental results show that compared to other works, the UHCIA achieves ∼23.6X of area reduction and ∼6.4X of power reduction, with high system throughput and biological real-time computations.

Performance and energy evaluation of dynamic adaptive deterministic routing algorithm for multicore architectures

Chip Multiprocessors (CMPs) leverage multiple processing units to improve computational speed and efficiency. Routing algorithms in NoC (Network-on-Chip) architectures ensure efficient data communication between these units, addressing challenges such as congestion, latency, and power consumption. This paper delves into an extensive analysis of the performance evaluation concerning the Dynamic Adaptive Deterministic (DyAD) routing for Network-on-Chip (NoC) and Wireless Network-on-Chip (WiNoC) configurations within the framework of a 64-core and 100-core multicore architecture. The evaluation involved a congestion threshold analysis of data transmission latency, the efficiency of network data throughput, and the amount of energy consumed. To substantiate our conclusions, we conducted simulations of the 64-core and 100-core mesh-based NoC and WiNoC architectures under the Video Image Processing System (VIPS) benchmark workload. These simulations were executed utilizing the Noxim simulator, a well-recognized tool acclaimed for its capacity to provide cycle-accurate simulations. Analyzing the simulation outcomes, it becomes evident that the DyAD routing approach for the 64-core and 100-core WiNoC architecture performs better in terms of network performance. It is characterized by enhanced capabilities at higher Packet Injection Rate (PIR) saturation loads, improved network throughput, and minimized latencies. This dominance is evident from its ability to handle heavier workloads and achieve lower delays in the investigated VIPS workload situations, compared to the 64-core and 100-core NoC multicore architecture.

Exploring distance-based wireless transceiver placements for wireless network-on-chip architecture with deterministic routing algorithms

Network-on-chip (NoC) technology is crucial for integrating multiple embed-ded computing cores onto a single chip. Consequently, this has led to the de-velopment of the wireless network-on-chip (WiNoC) concept, seen as a promis-ing strategy to overcome scalability issues in communication systems withinchips for future many-core architectures. This research analyses the impactof wireless transceiver subnet clustering on the hundred-core mesh-structuredWiNoC architecture. The study aims to examine the effects of distance-basedwireless transceiver placements on the transmission delay, network throughput,and energy consumption within a mesh wireless NoC architecture featuring ahundred cores, under specific routing strategies: X-Y, west-first, negative-first,and north-last. This research investigates the impact of positioning radio sub-nets at the farthest, farther, nearest, and closest positions within an architectureequipped with four wireless transceivers. The Noxim simulator was utilised tosimulate the analysed wireless transceiver placements within the hundred-coremesh-structured WiNoC designs, with the objective of validating the results.The architecture with the wireless transceivers positioned at midway proxim-ity (nearer and further) demonstrated the best performance, as evidenced by thelowest latencies for all evaluated deterministic routing algorithms, according tothe simulation outcomes.

Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems

With the emergence of cutting-edge hardware systems such as cloud computing, edge computing, and on-chip neural network accelerators, how to design advanced memory strategies to substitute the traditional ones for maximizing the potential performance of non-volatile memory (NVM) under the existing hardware conditions, has become an urgent research issue for both academia and industrial communities. It is promising and innovative to improve computer systems in the layer of data exchanging with the emerging advanced semiconductor devices. In the paper, to address the inefficiencies of write-intensive, high power consumption, low hit rate and so on, which exist in hybrid magnetic random access memory cache systems, three novel cache replacement strategies and two cache prefetching strategies are put forward. The proposed triple novel replacement strategies, including historical frequency and time judgments, duplicate data-aware deletion, and dynamic relevance factors computing, can be utilized to compensate for the shortcomings of the traditional least recently used replacement strategy, respectively. In the two novel prefetching strategies, region distribution parameters and Listnet ranking network are imported into the caching process, respectively, to achieve optimized hitting performance. The simulation results demonstrate that the proposed replacement strategies can achieve up to 61.76%, 84.91%, 56.49%, and 53.21% optimization of write count, hit rate, dynamic power, and IPC compared to the conventional one. The proposed prefetching strategy can achieve up to 91.27%, 49.25% hit rate and IPC optimization. Meanwhile, the synthetic evaluation of the replacement and prefetching strategies are elaborated in the paper, including multi-core characteristics, information entropy, interplays and the performance constraints between replacement and prefetching mechanism, which would facilitate more credible ideas for future memory inefficiencies management and strategy design.

A Survey of of Side-Channel Attacks and Mitigation for Processor Interconnects

With advancements in chip technology, the number of cores in modern commercial processors continues to rise, leading to increased complexity in interconnects and on-chip networks. This complexity, however, exposes significant security vulnerabilities, primarily in the form of side-channel and covert-channel exploits. Unlike other microarchitectural side-channel attacks, those leveraging on-chip interconnects utilize unique characteristics, allowing attackers to develop novel methods that can bypass existing effective defenses. In this paper, we present a comprehensive survey of current side-channel and covert-channel attacks based on processor-on-chip interconnects. We categorize these attacks into three types: contention-based, distance-based, and layout-based, according to the specific interconnect characteristics they exploit, and discuss corresponding countermeasures for each. Finally, we provide an outlook on future development trends in processor interconnect side channels. This survey is the first to specifically focus on interconnect-based side channels in processors.

NxtSPR: A deadlock-free shortest path routing dedicated to relaying for Triplet-Based many-core Architecture

Deadlock-free routing is a significant challenge in Network-on-Chip (NoC) design as it affects the network’s latency, power consumption, and load balance, impacting the performance of multi-processor systems-on-chip. However, achieving deadlock-free routing will routinely result in expensive overhead as previous solutions either sacrifice performance or power efficiency to proactively avoid deadlocks or impose high hardware complexity to resolve deadlocks when they occur reactively. Utilizing the various characteristics of NoC to implement deadlock-free routing can be significantly more cost-effective with less impact on performance. This paper proposes a relay routing algorithm (NxtSPR) with a shortest path property and a deadlock prevention mechanism based on a synchronized Hamiltonian ring. The proposal is based on an in-depth study of the characteristics of a Triplet-Based many-core Architecture (TriBA) NoC. We establish various important topology-related theories and perform a formal verification (proof-based) for them. By utilizing the critical subgraph and apex of TriBA, NxtSPR can pre-calculate downstream nodes forwarding ports for packets by using a concise judgment strategy. This significantly reduces the computational overhead required for data transmission while optimizing the pipeline design of routers to decrease packet transmission latency and power consumption compared to other TriBA routing algorithms. We group the data transmissions according to the levels of maximum Hamiltonian edges a packet will traverse during its transmission life cycle. Independent data transmissions between groups can avoid mutual interference and resource competition, eliminating potential deadlocks. Gem5 simulation results show that, under the synthetic traffic patterns, compared to the representative (Table) and up-to-date (SPR4T) routing algorithms, NxtSPR achieves a 20.19%, 14.76%, and 5.54%, 4.66% reduction in average packet latency and per-packet power consumption, respectively. Moreover, it has an average of 18.50% and 4.34% improvement in throughput, as compared to them. PARSEC benchmark results show that NxtSPR reduces application runtime by up to a maximum of 22.30% and 12.82% compared to Table and SPR4T, and running the same applications with TriBA results in a maximum runtime reduction of 10.77% compared to 2D-Mesh.

Experimental demonstration of a silicon four-mode (de)multiplexer based on cascaded triple-waveguide couplers

Silicon photonics based on-chip mode-division multiplexing (MDM) is an appealing technology for enhancing the interconnect capacity in both short- and long-haul optical communication. Here, a silicon four-mode (de)multiplexer [(De)MUX] is proposed, optimized, fabricated, and characterized for on-chip MDM systems, based on three cascaded triple-waveguide couplers (TWCs), with coupling lengths below 24.25 µm. A four-mode MDM-link consisting of two back-to-back mode-(De)MUXs was fabricated and measured, yielding a crosstalk of less than −15.0dB over a bandwidth wider than 72.6 nm for four modes. In addition, the TWC based mode (De)MUX demonstrates a 1-dB bandwidth greater than 40 nm, and can be considered as a robust component for multimode on-chip networks.