Network Interface Card Research Articles

A Design of A Mobile Remote Monitoring PDA Prototype Base on Embedded Linux with Wireless LAN Environment

Objective. Telemedicine uses common technologies that provide a conduit for information exchange between physicians nurses and patients. In addition to patient records, medical professionals can obtain vital signs and other reference data through telemedicine applications. also, recent advancement in RF technology and wireless communications has enabled the development of noble networks. Mobile telemedicine involves more than just communicating via mobile phone of PDA that sends and receives medical data on Portable Internet. Methods. This paper describes the design of a mobile telemedicine PDA prototype based on Embedded Linux that can be used to monitor the medical information using a single board computer(SBC). Results. The device hardware architecture consist of signal conditioning circuit, single chip micro-controller, LCD display and wireless network interface card(W-NIC). Embedded Linux was ported as its operating system and application software was developed QT/embedded 2.3.7. Conclusion. This system would be very useful for patients with chronic illness, especially in an emergent environment, and for containing medical cost in the aged society.

Wireless Handheld Computers in the Preclinical Undergraduate Curriculum

abstractThis report presents the results of a pilot project using wireless PDAs as teaching tools in an undergraduate medical curriculum. This technology was used to foster a transition from a passive to an interactive learning environment in the classroom and provided a solution for the implementation of computer-based exams for a large class. Wayne State Medical School recently provided model e570 Toshiba PocketPCs® (personal digital assistants or PDAs), network interface cards, and application software developed by CampusMobility® to 20 sophomore medical students. The pilot group of preclinical students used the PDAs to access web-based course content, for communication, scheduling, to participate in interactive teaching sessions, and to complete course evaluations. Another part of this pilot has been to utilize the PDAs for computer-based exams in a wireless environment. Server authentication that restricted access during the exams and a proctoring console to monitor and record the PDA screens will be described in this report. Results of a student satisfaction survey will be presented.

Design and performance of an enhanced IEEE 802.11 MAC protocol for multihop coverage extension

Ad hoc communication is gaining popularity, not only for pure ad hoc communication networks but also as a viable solution for coverage extension in wireless networks. Especially for upcoming WLAN hotspots, this is an interesting option to decrease installation costs. In this article we introduce a new MAC protocol that needs only marginal changes to the standard and enables efficient multihop networking. We advocate the use of multiple IEEE 802.11 channels, where one channel is reserved as a common signalling channel for the task of assigning the others (data channels) among wireless terminals. The proposed MAC protocols are based on a four-way handshake over the common signalling channel, while data transmission occurs on a dedicated channel. We propose a further optimization applying multiple wireless network interface cards. This improvement in performance comes at the price of a slightly more complex hardware. Two different simulation models are implemented to investigate our approach. The first model investigates the MAC protocol and its improvements, while the second model analyzes the multihop performance in terms of delivery ratio and transmission delay. BY means of numerous simulations we present the performance of our MAC approach in comparison with two standard approaches in terms of bandwidth, packet delivery, and transmission delay. For our performance evaluation we apply the IEEE 802.11a technology, but we note that our approach can also be used for IEEE 802.11b.

Scalable Bulk Data Transfer in Wide Area Networks

Bulk data transfer in wide area networks (WAN) requires scalable and high network bandwidth. In this paper, we identify a number of the scalability limitations that affect the full utilization of peak theoretical network bandwidth. In addition, we study and classify different offered approaches to overcome some of the identified limitations and increase network bandwidth among Grid components in WAN. With these limitations in mind, we study and evaluate the scalability and flexibility of a UDP-based multiple-network-interface socket (MuniSocket) model in WAN. The MuniSocket model is a middleware layer between the distributed applications and the multiple networks and system resources available. MuniSocket utilizes existing system resources, network interface cards, and network links to provide a scalable, reliable and high bandwidth network solution for data-intensive distributed applications, thus eliminating most of the identified limitations.

Analysis of TCP's computational energy cost for mobile computing

In this paper we present results from a measurement study of TCP (Transmission Control Protocol) running over a wireless link. Our primary goal was on obtaining a breakdown of the computational energy cost of TCP at the sender and receiver (excluding radio energy costs) as a first step in developing techniques to reduce this cost in actual systems. We analyzed the energy consumption of TCP in FreeBSD 5 running on a wireless laptop. Our initial results showed that 60 - 70% of the energy cost (for transmission or reception) is accounted for by the Kernel -- NIC (Network Interface Card) copy operation. Of the remainder, 15% is accounted for in the copy operation from user space to kernel space with the remaining 15% being accounted for by TCP processing costs. We then further analyzed the TCP processing cost and determined the cost of computing checksums accounts for 20 -- 30% of TCP processing cost.

High‐speed bulk data transfer architecture for Gbit/s throughput

AbstractWhen bulk data is transferred between end hosts over an IP network, a known problem is the limited throughput obtained at the application level due to the memory copy processing load between the kernel buffer and the user buffer depending on the operating system. To solve this problem, in this paper we propose a high‐speed bulk data transfer architecture called Network Direct Memory Access (Network DMA) and describe its design, implementation, and test results. The purpose of Network DMA is to be a transport function installed on a network interface card (NIC) and to achieve high‐speed and reliable data transfers over a network between the user buffers of the end hosts without requiring operating system‐specific processing. An application will use the data transfer function provided by a new interface capable of directly specifying the send destination host and the target transfer buffer. Based on the proposed architecture, we developed a 622‐Mbit/s ATM NIC and Gigabit Ethernet NIC incorporating the Network DMA. The ATM NIC we developed achieved a continuous transfer throughput of 540 Mbit/s (99% bandwidth usage efficiency at the application level) in data transfer tests between general‐purpose PCs. The Gigabit Ethernet NIC achieved an 800 Mbit/s continuous transfer throughput. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 86(11): 57–65, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.10107

Analysis of a prototype intelligent network interface

AbstractWith a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies found in their more expensive supercomputer counterparts. Many users find that what Beowulf clusters lack in technology, they more than make up for with their significant cost advantage. In this paper, an architectural extension that adds reconfigurable computing to the network interface of Beowulf clusters is proposed. The proposed extension, called an intelligent network interface card (or INIC), enhances both the network and processor capabilities of the cluster, which has a significant impact on the performance of a crucial class of applications. Furthermore, for some applications, the proposed extension partially compensates for weaknesses in the PC memory subsystem. A prototype of the proposed architecture was constructed and analyzed. In addition, two applications, the 2D Fast Fourier Transform (2D‐FFT) and integer sorting, which benefit from the resulting architecture, are discussed and analyzed on the proposed architecture. Specifically, results indicate that the 2D‐FFT is performed 15–50% faster when using the prototype INIC rather than the comparable Gigabit Ethernet. Early simulation results also indicate that integer sorting will receive a 21–32% performance boost from the prototype. The significant improvements seen with a relatively limited prototype lead to the conclusion that cluster network interfaces enhanced with reconfigurable computing could significantly improve the Beowulf architecture. Copyright © 2003 John Wiley & Sons, Ltd.

Design of a multigigabit optical network interface card

High-speed optical data links enable local area networks (LANs) that operate at data rates above 10 Gb/s. Various network, protocol and switch architectures have been proposed that use these links. The optical network interface card (ONIC) is an important component for demonstrating efficient application of these architectures. In this paper, we describe the design of a programmable ONIC that interfaces a 12-channel gigabit parallel optical link module with a 64-bit/66-MHz PCI computer bus. Hardware programmability (using FPGAs) enables the ONIC to efficiently implement different communication protocols. For hardware testing, the ONIC hardware was programmed for bit error rate (BER) analysis. In continuous operation at 8 Gb/s for 30 days through a 1-m fiber, no errors occured. For application testing, a custom ONIC software driver was developed. We used this driver to demonstrate message passing between applications running on two ONIC-equipped servers. The ONIC design provides a low-cost solution that can be readily adapted for application and device specific requirements. The use of ONIC in a free-space optical switch system is described here.

Firmware-Level Latency Analysis on a Gigabit Network

Gigabit networks are equipped with “increasingly” intelligent network interface cards, and the firmware running in the cards does various tasks related to end-to-end communication. For an accurate performance evaluation of gigabit networks, it is very important to characterize and quantify the firmware. However, the firmware has been neglected in the latency analyzes of network protocols. This paper presents an in-depth latency analysis of Myrinet. Our findings include that the major bottleneck is the network interface card itself. This is true especially for so-called lightweight user-level protocols (such as BPI of Myrinet) designed for high-speed communication. Although BPI is very lean and efficient in the host, its sending throughput becomes similar to UDP. This result is very unexpected and surprising. Through firmware-level measurements, we identify that the cause of bottleneck is the DMA performance.

Q-Soft: software framework for QoS support in home networks

In this paper we report the development and implementation of Q-Soft, a Quality of Service (QoS) software framework, that provides QoS support for real-time (RT) applications in wired and wireless home networks. RT applications such as voice and video are delay and delay variation sensitive, i.e., in case the packets incur large delays and delay variation, the quality of the application is severely degraded (e.g., the video is choppy and the voice is not clear). Successful launching of RT applications necessitates end-to-end QoS guarantees in terms of bandwidth, bounded delays and delay jitter. Q-Soft is independent of the network interface card and of the multimedia applications we run. The experimental results of our solution were obtained on a PC-Windows-based testbed consisting of a home network (wired or wireless) connected to the Internet via a residential gateway. The experimental results we have obtained provide evidence that our solution provides QoS service support for multimedia applications.

Making Data Flow

Making Data Flow

The personal Internet security guidebook: keeping hackers and crackers out of your home

Introduction Virus Worms Trojan Port Scanning File Share Attacks DOS Operating Systems (OS) Attacks Scams Chapter 1 - The Internet Beginning of TCP/IP TCP/IP and the Internet OK, Back to Reality Why Ethernet? Chapter 2 - Got DSL, Got Cable, May Have Trouble (Connecting to the Internet today) The Internet and the Home User The Personal Computer at Home: The Business Computer at Home: Connection Types Dial-Up ISDN DSL Cable Modem Chapter 3 - Connecting Your Home Network to the Internet Connection Types Network Interface Cards Setting Up the NIC HUB Routers What about Networking my MAC? Personal Firewalls Chapter 4 - Securing Your DSL, Cable Modem and Dial Up Connection Virus Review Law Software Attacks Against You and Your Pets Good Security Practices List of Death The Approach A Quick Overview on a Wireless Home Network Network Card or the PC The Access Point Dial-up Configuration Settings WinIPCfg IPConfig Junk and The Junk The Spam Chapter 5 - Physical Security and Insurance Where are the risks? Theft Prevention Devices Alarms Anti-theft Security Enclosures Automatic Alert System Other Considerations Insurance PC Security Checklist Chapter 6 - Data Protection Windows 2000 EFS A Vendor Solution (Gatekeeper) Smart Cards Chapter 7 - Keep Your Data Private Who is Keeping US Safe How Are You Being Tracked? The FBI and Carnivore Privacy Tools Privacy References Chapter 8 - Encryption For Your PC A History of Cryptography Key Types How a Public-Private encryption system works RSA - Public and Private Key PGP Digital Signatures S/MIME Digital Certificates How It All Works Now the Packet Sniffer Securing the Link with SSL Using and Managing Certificates Reference books about Encryption Security Hardware and Software Reference Section Encryption Filters General Protection Personal Firewall User Authentication Virus Protection TCP/IP Reference ARP and Routing Ports DHCP Glossary of Terms

Testing ethernet networks for the ATLAS data collection system

This paper reports recent work on ethernet traffic generation and analysis. We use gigabit ethernet network interface cards (NICs) running customized embedded software and custom-built 32-port fast ethernet boards based on field programmable gate arrays (FPGAs) to study the behavior of large ethernet networks. The traffic generation software is able to accommodate many traffic distributions with the ultimate goal of generating traffic that resembles the data collection system of the ATLAS experiment at CERN, Geneva, Switzerland. Each packet is time stamped with a global clock value and, therefore, we are able to compute an accurate measure of the network latency. Various other information collected from the boards is displayed in real time on a graphical interface. This work provides the tools to study a test bed representing a fraction of the 1600 ATLAS detector readout buffers and 600 Level 2 trigger central processing units (CPUs) using a combination of the fast ethernet boards and the gigabit ethernet NICs.

Multicast grouping for data distribution management

The High Level Architecture's (HLA) Data Distribution Management (DDM) services are the most recent in a succession of systems designed to reduce the amount of data received by individual simulations in large-scale distributed simulations. A common optimization in these interest management systems is the use of multicast groups for sending data to a selected subset of all potential receivers. The use of multicast has met with considerable success in this application. However, its use to date has relied on a priori knowledge of communication patterns between simulations and static assignment of multicast groups to these patterns. As larger, more complex, and less predictable simulations are built, the need has arisen for more efficient use of multicast groups as they are a restricted resource [3Com Corporation, Scaling Performance and Managing Growth with the CoreBuilder 3500 Layer 3 Switch (available at http://www.3com.com/products/dsheets/400347a.html) lists a limit of 6 K, the highest number identified while Synthetic Theater of War (STOW) (D. Van Hook, RITN IM and IM history, personal communication, January 1996) had a hardware limit of approximately 1000. A typical workstation network interface card has only a few (H. Abrams, Extensible interest management for scalable persistent distributed virtual environments, Ph.D. Dissertation, Naval Postgraduate School, December 1999)]. This paper presents two algorithms for performing grouping, and the message delivery time improvements resulting from applying the algorithms to selected data sets.

Architectures for Heterogeneous Multi-Tier Networks

Next-generation wireless computing platforms will contain flexiblecommunications capabilites. At Rice University,the Rice Everywhere NEtwork (RENÉ) project is investigating a multi-standard, multi-tierintegration of W-CDMA cellular systems, high speed wireless LANs, and home wireless networks.There are many challenges in mapping these advanced communicationalgorithms to real-time hardware computing platforms.In this paper, we present current work on the developmentof a reconfigurable baseband physical layer containing DSP processorsand FPGA accelerators. Our goal is the design of amulti-tier network interface card (mNIC) which is capableof exploiting efficient, low-power reconfiguration.

Design Alternatives for Virtual Interface Architecture and an Implementation on IBM Netfinity NT Cluster

The Virtual Interface Architecture (VIA) specification has been developed to standardize user-level network interfaces that provide low-latency, high-bandwidth communications. Few hardware and software implementations of VIA exist. Since the VIA specification is flexible, different choices exist for implementing various components of VIA such as doorbells, address translation methods, and completion queues. Although previous studies have evaluated the overall performance of different VIA implementations, there has not been a comparative study on the performance of VIA components. In this paper, we evaluate and compare the performance of different implementations of essential VIA components. We discuss the pros and cons of each design approach and describe the required support for implementing each of them. Then, we discuss an experimental implementation of the Virtual Interface Architecture for the IBM SP Switch-Connected NT cluster, one of the newest clustering platforms available. We discuss different design issues involved in this implementation. In particular, we explain how the virtual-to-physical address translation is implemented efficiently with a minimum Network Interface Card (NIC) memory requirement. We show how caching the VIA descriptors on the NIC can reduce the communication latency. We also present an efficient scheme for implementing the VIA doorbells without any hardware support. We provide a comprehensive performance evaluation study and discuss the impact of several hardware improvements on the performance of our implementation. The performance of the implemented VIA surpasses that of other existing software implementations of the VIA and is comparable to that of a hardware VIA implementation. The peak measured bandwidth for our system is 101.4MBytes/s and the one-way latency for short messages is 18.2μs.

Study of the Medium Message Performance of BIP/Myrinet

The Basic Interface for Parallelism (BIP) [1] is a low-level communication system for Myrinet programmable network interface cards (NIC). On one hand BIP has proven that a very small latency and a very large throughput can be delivered. On another hand hardware implementations, like Giganet or NICs that implement the Scalable Coherent Interface (SCI), demonstrate very good performance for medium-sized messages. Our aim in this paper is to study how the programmable NICs can compare with the hardware solutions for medium-sized messages. We built a very precise model of the pipeline behavior driven by the NIC program in order to identify the bottlenecks. The results show that the pipeline quality is critical. We have developed an adaptive strategy as in [2] and then introduced it in BIP. Experiments show up to a two-fold gain over the previous BIP results and reach performances above the hardware solutions.

Event building in an intelligent network interface card for the LHCb DAQ system

LHCb is an experiment being constructed at CERN's Large Hadron Collider accelerator for the purpose of studying precisely the charge and parity violation parameters in the B-B meson system. Triggering poses special problems since the interesting events containing B-mesons are immersed in a large background of inelastic p-p reactions. Therefore, a four-level triggering scheme (Level-0 to Level-3) has been implemented. Full event building is performed between Level-1 and Level-2. Powerful embedded processors, used in modern intelligent network interface cards, are attractive to use to handle the event-building protocol in the high-speed data-acquisition system. The implementation of an event-building algorithm developed for a specific gigabit Ethernet network interface controller is presented, and results from performance measurements are discussed.

STUDY OF THE MEDIUM MESSAGE PERFORMANCE OF BIP/MYRINET

The Basic Interface for Parallelism (BIP) [1] is a low-level communication system for Myrinet programmable network interface cards (NIC). On one hand BIP has proven that a very small latency and a very large throughput can be delivered. On another hand hardware implementations, like Giganet or NICs that implement the Scalable Coherent Interface (SCI), demonstrate very good performance for medium-sized messages. Our aim in this paper is to study how the programmable NICs can compare with the hardware solutions for medium-sized messages. We built a very precise model of the pipeline behavior driven by the NIC program in order to identify the bottlenecks. The results show that the pipeline quality is critical. We have developed an adaptive strategy as in [2] and then introduced it in BIP. Experiments show up to a two-fold gain over the previous BIP results and reach performances above the hardware solutions.

Design and analysis of a scalable optical interconnection network for a computer cluster

This paper describes the dual-layer scalable optical intercon- nection network being developed at Tianjin University. The top layer of the network is a multiwavelength bidirectional optical bus, which has large bandwidth and low latency. The bus is made up of passive com- ponents. No wavelength-tunable devices are used. As a result, the bus has a low communication latency that is mainly determined by the optical fiber length. The sublayer of the network is a single-wavelength ring, which has low communication latency and high scalability. In each ring, a wavelength routing node is designed for data transmission between the ring and the optical bus. Each node computer is connected to the ring through an optical network interface card. The communication latency inside the ring is decreased by using synchronous pipelining transmis- sion. © 2001 Society of Photo-Optical Instrumentation Engineers.