Negative Voltage Stress Research Articles

Studies of the quality of GdSiO–Si interface

In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods ( C– V, I– V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C– V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.

Negative Bias Temperature Instability “Recovery" under Negative Stress Voltage with Different Oxide Thicknesses

Different phenomena are observed under negative gate voltage stress which is smaller than the previous degradation stress in PMOSFETs with different oxide thicknesses. We adopt the real time method to make a point of the drain current to study the degradation and recovery of negative bias temperature instability (NBTI). For the device with thin oxide, recovery phenomenon appears when smaller negative voltage stress was applied, due to the more influencing oxide charges detrapping effects than the interface states. For the device with thick oxide, not recovery but degradation phenomenon comes forth. As many charges are trapped in the deeper position and higher energy level in the oxide, these charges can not be detrapped. Therefore, the effect of the charge detrapping is smaller than that of the interface states in the thick oxide. The degradation presents itself during the ‘recovery’ time.

Application of high-k dielectric stacks charge trapping for CMOS technology

Abstract The effect of constant negative voltage stress on charge trapping and interface states of Al/HfO 2 /SiO x N y /Si structures are investigated. The reduction in the capacitance of C – t characteristics and a significant shift in C – V curves towards negative voltage axis reveal that the charge trapping/detrapping occurs at the Si/SiO x N y /HfO 2 interface and HfO 2 bulk. However, there is a relative increase in gate leakage current as a function of the voltage stress and time, owing to the trap-assisted tunnelling. It is suggested that these traps are probably Hf–OH neutral centers, originating from the breaking of bridging Si–OH and Si–NH bonds by mobile H + protons. This has potential application in non-volatile CMOS memory devices.

Modeling and measuring transient discharge current of microelectromechanical switches after dielectric charging by voltage stress

Dielectric charging effect in microelectromechanical systems has been studied using transient discharge current measurements after applying both positive and negative voltage stresses. An analytical model considering a single trap in the dielectric has been developed after the derivation of an equivalent circuit of the switch. The total amount of charge trapped can be measured and also the main parameters of the trap and dielectric layer. It is shown that the sign of the stress voltage is important in terms of the amount of charge trapped and of the trap properties

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.

Stress-Polarity-Independent Negative Threshold Voltage Shift in HfO2/TiN P-Channel Metal Oxide Semiconductor Field-Effect Transistor

The stress-polarity-independent threshold voltage shift characteristics of HfO2 p-channel metal oxide semiconductor field-effect transistor (pMOSFET) with a TiN/p+ polycrystalline silicon electrode have been investigated. Positively charged defect states are shown to be generated under both positive and negative voltage stresses in HfO2 pMOSFET. Further enhancement of positive threshold voltage shift under the positive voltage stress is observed when HfO2 thickness is increased. In the analyses by charge pumping measurement, significant generation and relaxation of the interface state during the positive voltage stress and relaxation cycle were observed near the HfO2/SiO2 interface. This suggests that the generation of positively charged defect states under a positive voltage stress is related to traps in the HfO2 layer rather than in the interfacial SiO2 layer.

Determination of the contribution of defect creation and charge trapping to the degradation of a-Si:H/SiN TFTs at room temperature and low voltages

In this paper is presented a qualitative investigation upon the mechanisms that cause the shift of the electrical parameters in thin film transistors (TFT). The transistors are made of amorphous hydrogenated silicon (a-Si:H) as active semiconductor layer and substoichiometric silicon nitride (SiN) as gate insulator. The work refers to the degradation at room temperature and low positive and negative gate voltage stresses. The electrical parameters: threshold voltage (Vth), subthreshold swing (S) and flat-band voltage (Vfb) have been determined from the dependence of the drain current on gate voltage (Id–Vg) and the dependence of the capacitance on the gate voltage (C–Vg) measurements as function of stress time and bias.

Rigidité diélectrique d'un interface gaz–support avec contaminant métallique dans l'air sec et ses mélanges avec le SF6

In this paper, we conduct a series of experiments aimed at analysing the dielectric properties of compressed dry air, and some SF6–air mixtures up to 700 kPa, under application of AC 50 Hz and lightning impulse (LI) 1.2 μs/50 μs voltage. The investigations were carried out by using a cylindrical spacer model with an adhering particle on the surface under homogenous field conditions. We measure the partial discharges (PD) propagation characteristics under LI voltage stress, as well as the PD inception voltage and the flashover voltage for the contaminated particle. We also investigate the surface charge accumulation on the spacer surface under contaminated particle conditions. The results of the experiments reveal the influence a conducting particle has on the determined flashover field strength, for SF6–air mixtures compared with pure, compressed dry air. This influence is discussed for different particle lengths, but also for three different particle positions in the gap. Pure dry air achieves a higher dielectric strength when the particle gets into contact with the high voltage electrode, under negative LI voltage stress. The same result is obtained for the SF6–air mixtures, when the particle is located in the middle of the gap, as floating electrode on the spacer surface. The reported results contribute to the improvement of the models of breakdown through the interface gas–solid isolator. The application of these models should offer the possibility for considering the use of dry air, or its mixtures with SF6 which, normally have a lower relative global warming potential than pure SF6.[Traduit par la Rédaction]

Dielectric reliability of stacked Al 2O 3–HfO 2 MIS capacitors with cylinder type for improving DRAM data retention characteristics

Dielectric reliability in Al 2O 3(2–3.1nm)–HfO 2(3nm) stack capacitor with Metal–Insulator–Si(MIS) structure is investigated in this paper. We propose an optimized capacitor process through the Time–Dependent Dielectric Breakdown (TDDB) data under various process conditions. Furthermore, due to asymmetric current at both negative and positive voltage stress polarities, we show different lifetime extrapolation by a fluence–driven model. As a result, the maximum allowed operating voltage is projected to be 1.7V (failure rate 10ppm during 10year @ 85°C) for Data “0” retention lifetime.

Thin Oxide Breakdown Mechanism of Constant Voltage Stress on MOSFETs

The breakdown mechanism of constant-voltage stress in MOSFETs has been investigated. The results show that the transient evolution of stress current dominates the breakdown mechanism of the thin oxide. Due to the stress current decreasing with time induced by trapped charges, the trapped charge increases with stress time, i.e. proportional to Ts0.4. As the results indicate, the relation between trapped charges and time-to-breakdown, the trapped charge generation rate could be obtained. By investigating stress-induced degradations, the impacts of positive constant voltage stress and negative constant voltage stress for device degradation are also analyzed and compared.

Experimental study of the quasi-breakdown failure mechanism in 4.5 nm-thick SiO 2 oxides

In this study, we have investigated the electrical properties of the failure mode referred as quasi-breakdown or soft-breakdown in MOS capacitors on p-type substrate with an oxide thickness of 4.5 nm. Quasi-breakdown appears during high field stresses as a sudden increase between two and four orders of magnitude in the gate current over the whole gate voltage range, but remains undetected in C( V) characteristics between 20 Hz and 100 kHz. Quasi-breakdown was systematically triggered during negative gate voltage stresses after a threshold between 10 and 15 C/cm 2 was reached in the injected charge, this threshold being independent of the stressing oxide field. A very weak temperature dependence and a low frequency noise in the gate current were also observed. The I( V) characteristics are found to follow a first-order exponential law versus the gate voltage, indicative of a direct tunneling process, which could result from a local lowering of the oxide thickness resulting from a sudden metal/isolant transition in a localized region of the oxide near the anode due to oxide defects.

Memory effects of silicon-implanted oxides for electrically erasable programmable read-only memory applications

The memory effects of silicon-implanted oxides are reported in this letter. Due to the trap-like characteristics of the implanted silicon, hysteresis capacitance-voltage loops have been measured after voltage pulse stressing. A positive voltage pulse leads to a positive shift of the capacitance-voltage curve, while a negative voltage stress results in a negative drift. It was found that using these Si-implanted oxides, writing/erasing operations of electrically erasable programmable read-only memories could be realized by applying short voltage pulses (e.g., 100 ns, ±12–16 V). Moreover, excellent retention characteristics were also detected for these memory devices. The implanted silicon alters the conduction mechanism such that the I-V behavior does not follow the Fowler–Nordheim tunneling. The implantation process did not yield noticeable degradation to the oxide quality; and a lifetime over 10 yr can be achieved even with ±16 V stressing.

Breakdown process of a rod-to-plane gap in atmospheric air under DC voltage stress

Discharge phenomena were observed under chopped or steady state DC voltage application. A still camera and two photomultipliers were used to record and measure the development of the electrical breakdown in a normal air gap. The breakdown process under both positive and negative DC voltage stress differs from that under impulse voltage. In the case of DC voltage, space charge is produced by corona discharges prior to the complete breakdown, which affects the breakdown process significantly. >

Dielectric breakdown wearout limitation of thermally-grown thin-gate oxides

Gate oxide wearout on thermally grown 60–200 A ̊ SiO 2 films in a polycrystalline Si (phosphorus doped)/SiO 2/Si structure was studied by examining time-dependent dielectric breakdown (TDDB) under positive and negative voltage stresses. TDDB data on temperature, electric field and gate area were evaluated and wearout limitation for thin gate oxide films was estimated. TDDB lifetimes for negative voltage were 2–3 orders shorter than those for positive voltage, when compared under the same electric field. This voltage polarity dependence was enhanced with decreasing oxide thickness. When compared under the same voltage, TDDB lifetimes for negative voltage were longer than those for positive voltage, caused by taking into account the flat-band voltage and the silicon surface potential bending. It was predicted that thin oxide films were basically highly reliable for both positive and negative voltages. 60 and 100 Å oxide films can be used under 3 and 5 V operating voltages, respectively, while retaining 10 year lifetimes defined by 0.01% failures.

Stress voltage polarity dependence of thermally grown thin gate oxide wearout

Gate oxide wearout for thermally grown 57-190-A SiO/sub 2/ films in a polycrystalline silicon-SiO/sub 2/-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm/sup 2/ constant current with positive and negative voltages at 250 degrees C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>