Negative Threshold Voltage Shift Research Articles

Origin and Recovery of Negative VTH Shift on 4H–SiC MOS Capacitors: An Analysis Based on Inverse Laplace Transform and Temperature-Dependent Measurements

SiC power MOSFETs are reported to suffer from both positive and negative threshold voltage shifts. Positive shift is well understood in the literature and attributed to electron trapping in near interface oxide traps (NIOTs). Negative shift is explained by hole generation and trapping in the oxide via impact ionization favored by the strong oxide field. However, studies on negative shift are still ongoing, and the origin and nature of the process are not fully understood. This study advances the comprehension of negative threshold voltage shift by investigating MOS capacitors subject to positive bias stress.We demonstrate that: a) a significant negative threshold shift is observed when the electric field is greater than 7.5 MV/cm; b) the detected shift is not recoverable at zero bias. Recovery can be obtained only by applying a positive gate voltage indicating a field-driven detrapping process. c) Trap-state mapping measurements were carried out to extract the activation energy of the detrapping processes, and a weak thermal activation was observed.Results collected within this paper indicate that holes are trapped at deep centers, and thermal detrapping is not possible. Hole release is only possible when a high field is applied to the insulator, possibly due to the recombination between leaking electrons and trapped holes.

Cation doping strategy for improved carrier mobility and stability in metal-oxide Heterojunction thin-film transistors

The heterojunction channel architecture has emerged as a viable solution to enhance the performance of metal-oxide thin-film transistors (TFTs), addressing the performance limitations of single-channel counterparts. However, carrier mobility enhancement through a channel thickness design often encounters significant challenges such as the negative threshold voltage (Vth) shift. In this study, we present a cation doping strategy, designed to regulate Vth shift while simultaneously boosting carrier mobility in zinc-tin-oxide (ZTO)-based heterojunction TFTs. A comprehensive investigation of ZTO-based semiconductors was conducted to explore the impact of cation doping on the energy band structure and to find an optimal heterojunction channel structure for high carrier mobility and stability. The resulting ZTO/Ti-doped ZTO (Ti:ZTO) heterojunction TFTs demonstrated a field-effect mobility of 39.7 cm2/Vs, surpassing the performance of ZTO TFTs (16.1 cm2/Vs), with a minimal change in the Vth. Furthermore, the ZTO/Ti:ZTO TFTs exhibited enhanced bias-stress stability compared to the ZTO TFTs. We attribute the improved mobility and stability to the electron accumulation near the oxide channel heterointerface facilitated by band bending and defect passivation effect arising from the Ti:ZTO back-channel layer, respectively.

Stability and gap states of amorphous In-Ga-Zn-Ox thin film transistors: Impact of sputtering configuration and post-annealing on device performance

Stability of amorphous In-Ga-Zn-Ox (a-IGZO) thin-film-transistors (TFTs) is studied from a viewpoint of gap states, associated with oxygen-related defects and structural disordering. The a-IGZO gap states are controlled through the film preparation by magnetron sputtering under two different configurations and post-annealing in oxygen atmosphere. The distribution of gap states is then evaluated from the subgap absorption spectrum, which is measured by a constant photocurrent measurement technique. With this known distribution, a-IGZO TFTs are fabricated, and the stability of the TFT performances is examined through the negative bias induced stability (NBIS) experiments. The results suggest that a negative threshold voltage shift, induced by NBIS, is improved by reducing the density of gap states, i.e., narrowing the gap state distribution. The reduction of gap states also contributes to the improvement of subthreshold swing.

Evaluation of p-GaN HEMTs degradation under high temperatures forward and reverse gate bias stress

In this study, the degradation behavior and physical mechanism of the p-GaN HEMT devices under high-temperature gate bias (HTGB) with +5 V and −5 V were investigated. The DC characteristics show that the device after forward HTGB stress exhibits an obvious negative threshold voltage (Vth ) shift, while the device after reverse HTGB exhibits a negligible shift. The following explanations could be given for the deterioration mechanism: a portion of the two-dimensional hole gas (2DHG) accumulated in the p-GaN layer at the p-GaN/AlGaN interface under long-term forward bias may fill the trap in the AlGaN layer through the tunneling effect. In addition, the drain-source on-resistance of the device had increased after +5 V HTGB stress, and a distinct decrease of accumulated capacitance was observed in the Cg -Vg curve. It indicates a degradation of the gate quality of the device after applying a forward-biased HTGB stress.

Reliability Assessment of On-Wafer AlGaN/GaN HEMTs: The Impact of Electric Field Stress on the Mean Time to Failure.

We present the mean time to failure (MTTF) of on-wafer AlGaN/GaN HEMTs under two distinct electric field stress conditions. The channel temperature (Tch) of the devices exhibits variability contingent upon the stress voltage and power dissipation, thereby influencing the long-term reliability of the devices. The accuracy of the channel temperature assumes a pivotal role in MTTF determination, a parameter measured and simulated through TCAD Silvaco device simulation. Under low electric field stress, a gradual degradation of IDSS is noted, accompanied by a negative shift in threshold voltage (ΔVT) and a substantial increase in gate leakage current (IG). Conversely, the high electric field stress condition induces a sudden decrease in IDSS without any observed shift in threshold voltage. For the low and high electric field conditions, MTTF values of 360 h and 160 h, respectively, were determined for on-wafer AlGaN/GaN HEMTs.

Influence of Channel Surface with Ozone Annealing and UV Treatment on the Electrical Characteristics of Top-Gate InGaZnO Thin-Film Transistors.

The effect of the channel interface of top-gate InGaZnO (IGZO) thin film transistors (TFTs) on the electrical properties caused by exposure to various wet chemicals such as deionized water, photoresist (PR), and strippers during the photolithography process was studied. Contrary to the good electrical characteristics of TFTs including a protective layer (PL) to avoid interface damage by wet chemical processes, TFTs without PL showed a conductive behavior with a negative threshold voltage shift, in which the ratio of Ga and Zn on the IGZO top surface reduced due to exposure to a stripper. In addition, the wet process in photolithography increased oxygen vacancy and oxygen impurity on the IGZO surface. The photo-patterning process increased donor-like defects in IGZO due to organic contamination on the IGZO surface by PR, making the TFT characteristics more conductive. The introduction of ozone (O3) annealing after photo-patterning and stripping of IGZO reduced the increased defect states on the surface of IGZO due to the wet process and effectively eliminated organic contamination by PR. In particular, by controlling surface oxygens on top of the IGZO surface excessively generated with O3 annealing using UV irradiation of 185 and 254 nm, IGZO TFTs with excellent current-voltage characteristics and reliability could be realized comparable to IGZO TFTs containing PL.

Mitigating Heavy Ion Irradiation‐Induced Degradation in p‐type SnO Thin‐Film Transistors at Room Temperature

The study investigates the mitigation of radiation damage on p‐type SnO thin‐film transistors (TFTs) with a fast, room‐temperature annealing process. Atomic layer deposition is utilized to fabricate bottom‐gate TFTs of high‐quality p‐type SnO layers. After 2.8 MeV Au4+ irradiation at a fluence level of 5.2 × 1012 ions cm−2, the output drain current and on/off current ratio (Ion/Ioff) decrease by more than one order of magnitude, field‐effect mobility (μFE) reduces more than four times, and subthreshold swing (SS) increases more than four times along with a negative shift in threshold voltage. The observed degradation is attributed to increased surface roughness and defect density, as confirmed by scanning electron microscopy (SEM), high‐resolution micro‐Raman, and transmission electron microscopy (TEM) with geometric phase analysis (GPA). A technique is demonstrated to recover the device performance at room temperature and in less than a minute, using the electron wind force (EWF) obtained from low‐duty‐cycle high‐density pulsed current. At a pulsed current density of 4.0 × 105 A cm−2, approximately four times increase in Ion/Ioff is observed, 41% increase in μFE, and 20% decrease in the SS of the irradiated TFTs, suggesting effectiveness of the new annealing technique.

Total-Ionizing-Dose Effects at Ultrahigh Doses in AlGaN/GaN HEMTs

Total-ionizing-dose effects in AlGaN/GaN HEMTs are evaluated by DC and low frequency noise measurements. Devices with and without passivation layers are irradiated with 10-keV X-rays up to 100 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) under different bias conditions. Irradiated devices show significant electrical shifts in threshold voltage and transconductance. At doses <10 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ), the TID-induced effects are related to the passivation of pre-existing acceptor-like defects via hole capture, which induces negative threshold voltage shifts and improvement of transconductance. At doses >10 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ), dehydrogenation of defects and impurity complexes leads to the creation of acceptor-like defects, which degrade the transconductance, shift positively the threshold voltage, and increase the low-frequency noise. Effects are enhanced in unpassivated devices and when the gate is biased at high voltage.

In Situ Radiation Hardness Study of Amorphous Zn-In-Sn-O Thin-Film Transistors with Structural Plasticity and Defect Tolerance.

Solution-processed metal-oxide thin-film transistors (TFTs) with different metal compositions are investigated for ex situ and in situ radiation hardness experiments against ionizing radiation exposure. The synergetic combination of structural plasticity of Zn, defect tolerance of Sn, and high electron mobility of In identifies amorphous zinc-indium-tin oxide (Zn-In-Sn-O or ZITO) as an optimal radiation-resistant channel layer of TFTs. The ZITO with an elemental blending ratio of 4:1:1 for Zn/In/Sn exhibits superior ex situ radiation resistance compared to In-Ga-Zn-O, Ga-Sn-O, Ga-In-Sn-O, and Ga-Sn-Zn-O. Based on the in situ irradiation results, where a negative threshold voltage shifts and a mobility increase as well as both off current and leakage current increase are observed, three factors are proposed for the degradation mechanisms: (i) increase of channel conductivity, (ii) interface-trapped and dielectric-trapped charge buildup, and (iii) trap-assisted tunneling in the dielectric. Finally, in situ radiation-hard oxide-based TFTs are demonstrated by employing a radiation-resistant ZITO channel, a thin dielectric (50 nm SiO2), and a passivation layer (PCBM for ambient exposure), which exhibit excellent stability with an electron mobility of ∼10 cm2/V s and aΔVth of <3 V under real-time (15 kGy/h) gamma-ray irradiation in an ambient atmosphere.

Toward High Bias‐Stress Stability P‐Type GaSb Nanowire Field‐Effect‐Transistor for Gate‐Controlled Near‐Infrared Photodetection and Photocommunication

AbstractThe bias‐stress instability of nanowires (NWs) field‐effect‐transistors (FETs), originated from the surface trappings, are challenging greatly the functionalization of III‐V group semiconductors in next‐generation electronics and optoelectronics. In this study, the solution‐processed high‐κ oxide dielectric shell is configured uniformly onto the surface of GaSb NWs, contributing to the excellent bias‐stress stability of as‐constructed p‐type NWFETs. Owing to the interdiffusion between Al and Ga, the oxide dielectric shell is Ga‐AlOx. With an optimal oxide dielectric shell, the as‐constructed p‐type GaSb NWFETs show an insignificant attenuation of on‐state current (within 10%) and a negligible negative shift of threshold voltage under 60 min continuous gate bias, which is far better than that of pristine GaSb NWFETs, resulting from the electric double layer effect. Benefiting from the excellent bias‐stress stability, when configured into the near‐infrared photodetector, NWFET exhibits desirable stability and gate‐controlled photodetection behaviors. Idark and Ilight are effectively modulated by gate voltage, resulting in gate‐controlled responsivity and gain under the illumination of 1550 nm laser. In the end, the as‐constructed bias‐stress stability NWFET demonstrates expected gate‐controlled photodetection imaging and photocommunication ability. The strategy of solution‐processed oxide dielectric shell promises high bias‐stress stability NWFETs for gate‐controlled photodetection and photocommunication.

Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate-source current and the gate-drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.

Interface dipole induced threshold voltage shift in the Al2O3/GaN heterostructure

The Al2O3/GaN heterostructure is a crucial component of GaN-based electronic and photonic devices, and the Al2O3/GaN interface quality plays an important role in determining the device performance. Here, using density functional theory, we confirmed that dipole formed at the Al2O3/GaN interface can be attributed to electron transfer and redistribution between Al2O3 and GaN. The formation of dipole was confirmed by X-ray photoemission spectroscopy. The dipole induced electric field at the interfaces of the Al2O3/GaN heterostructures result in negative threshold voltage (VTH) shifts of 2.3 and 1.2 V for the heterostructures without defects and with one Al interstitial (Ali) defect, respectively. On the other hand, the Ali defect can induce positive charges, resulting in negative VTH shifts. Therefore, an improvement in the interface quality (i.e., by eliminating the Ali defect) does not necessarily result in positive VTH shifts. This study reveals novel electronic properties of the Al2O3/GaN heterostructure and offers a path toward the achievement of GaN-based devices with engineered features.

Multiple effects of hydrogen on InGaZnO thin-film transistor and the hydrogenation-resistibility enhancement

As the most common external dopant of amorphous oxide semiconductors (AOSs), the hydrogen (H) exhibits great influences on the performance of AOS thin-film transistors (TFTs) and is almost inevitable during device fabrication. In this work, the multiple effects of H doping on the amorphous InGaZnO (IGZO) TFT were systematically investigated by experimental and theoretical calculation methods, and the hydrogenation-resistibility was further investigated. The electrical performances of the hydrogenated IGZO TFT were determined by the concentrations of H itself and oxygen vacancy (Vo). With increasing H content, it separately serves as defect suppressor, donor defect, donor/acceptor transition state and then acceptor defect, resulting in the improved subthreshold slope (SS), negative shift of threshold voltage (Vth), fluctuation of mobility (μFE), and limitation of on-state current (Ion), respectively. The Vo in IGZO is considered to provide the diffusion channel of H dopant, thus determining the H concentration and the electrical behaviors. Furthermore, the hydrogen-resistibility of IGZO was enhanced by using the fluorine (F) dopant to suppress the intrinsic Vo content and weaken the dissociation energy of H-related bonds. The F-IGZO TFT exhibits excellent stabilities even in the H-rich environment. The findings not only deepen the understanding and manipulation of H doping in AOS devices, but also broaden the application scopes.

Mechanical stress in a tapered channel hole of 3D NAND flash memory

Mechanical stress impact according to the taper angle in 3D vertical NAND flash memory (V-NAND) was investigated using technology computer-aided design simulation (TCAD). In the non-tapered V-NAND, the stress of the polysilicon channel is similar regardless of the number of layers and the position of the WL. On the other hand, in tapered V-NAND, as the taper angle decreases, the CD variation of the channel hole increases, and the compressive stress increases close to the lower WL. The compressive stress applied to the polysilicon channel produces a negative threshold voltage shift (ΔVth) due to conduction band lowering. In tapered V-NAND, the lower WL has a larger ΔVth than the upper WL, and a non-uniform Vth shift occurs. However, as the gate length of the tapered V-NAND is scaled down, the stress of the polysilicon channel is decreased, and the stress difference between the lower WL and upper WL is reduced; therefore, the non-uniform Vth shift is suppressed.

Influence of Bulk Doping and Halos on the TID Response of I/O and Core 150 nm nMOSFETs

The total ionizing dose sensitivity of planar 150 nm CMOS technology is evaluated by measuring the DC responses of nMOSFETs at several irradiation steps up to 125 krad(SiO2). Different TID sensitivities are measured for transistors built with different channel dimensions and operating voltages (I/O and core). The experimental results evidence strong relations between TID sensitivity and the doping profiles in the channel. I/O transistors have the highest TID sensitivity due to their thicker gate oxide and lower bulk doping compared with core devices. In general, narrow-channel devices have the worst degradation with negative threshold voltage shifts, transconductance variations and increased subthreshold leakage currents, suggesting charge trapping in shallow trench isolation (STI). The enhanced TID tolerance of short-channel core devices is most likely related to the increased channel doping induced by the overlapping of halo implantations. Finally, transistors fabricated for low-leakage applications exhibit near insensitivity to TID due to higher bulk doping used during the fabrication to minimize the drain-to-source leakage current.

Ultraviolet photodetectors based on Si-Zn-SnO thin film transistors with a stacked channel structure and a patterned NiO capping layer

Ultraviolet photodetectors (UVPDs) based on Si-Zn-SnO (SZTO) thin-film transistors (TFTs) with a stacked dual-channel layer (DCL) structure with different carrier concentration and NiO capping layer (CL) to alleviate the trade-off between dark current (I dark) and photocurrent (I ph) are reported. Experimental results show that under 275 nm irradiation, the proposed SZTO TFT UVPD with a 30 nm thick upper layer stacked on a 50 nm thick channel layer and a patterned NiO CL exhibit excellent photoresponsivity and photosensitivity up to 1672 A W−1 and 1.03 × 107 A A−1, which is about 272 and 137 times higher than conventional 30 nm thick single-channel layer SZTO TFT. These improvements are due to the use of a DCL which forms a high-low junction to reduce the effective channel thickness and increasing the space for UV illumination and the use of NiO CL lowers the I dark and causes a considerable negative threshold voltage shift under UV irradiation to significantly boost the I ph.

Localized strain relaxation effect on gamma irradiated AlGaN/GaN high electron mobility transistors

Strain localization in microelectronic devices commonly arises from device geometry, materials, and fabrication processing. In this study, we controllably relieve the local strain field of AlGaN/GaN HEMTs by milling micro-trenches underneath the channel and compare the device performance as a function of the relieved strain as well as radiation dosage. Micro-Raman results suggest that the trenches locally relax the strain in device layers, decreasing the 2DEG density and mobility. Intriguingly, such strain relaxation is shown to minimize the radiation damage, measured after 10 Mrads of 60Co-gamma exposure. For example, a 6-trench device showed only ∼8% and ∼6% decrease in saturation drain current and maximum transconductance, respectively, compared to corresponding values of ∼15% and ∼30% in a no-trench device. Negative and positive threshold voltage shifts are observed in 6-trench and no-trench devices, respectively, after gamma radiation. We hypothesize that the extent of gamma radiation damage depends on the strain level in the devices. Thus, even though milling a trench decreases 2DEG mobility, such decrease under gamma radiation is far less in a 6-trench device (∼1.5%) compared to a no-trench device (∼20%) with higher built-in strain.

Threshold voltage instability by charge trapping effects in the gate region of p-GaN HEMTs

In this work, threshold voltage instability of normally off p-GaN high electron mobility transistors has been investigated by monitoring the gate current density during a device on-state. The origin of gate current variations under stress has been ascribed to charge trapping occurring at different interfaces in the metal/p-GaN/AlGaN/GaN system. In particular, depending on the stress bias level, electrons (VG &amp;lt; 6 V) or holes (VG &amp;gt; 6 V) are trapped, causing a positive or negative threshold voltage shift ΔVTH, respectively. By monitoring the gate current variations at different temperatures, activation energies associated with the electrons and holes trapping could be determined and correlated with the presence of nitrogen (electron traps) or gallium (hole traps) vacancies. Moreover, the electrical measurements suggested the generation of a new electron-trap upon long-time bias stress, associated with the creation of crystallographic dislocation-like defects extending across different interfaces (p-GaN/AlGaN/GaN) of the gate stack.

Total Ionizing Dose and Annealing Effects on Shift for p-GaN Gate AlGaN/GaN HEMTs

A research of total ionizing dose and annealing effects on Schottky type p-GaN gate Al0.2Ga0.8N/GaN high electron mobility transistors (HEMTs) has been carried out. Devices with breakdown voltages of 100V/200V/650V were irradiated under Co-60 X-rays. Radiation doses reach to a total amount of 500 krad (Si) with dose rate of 50 rad(Si)/s under gate biases of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{GS}=0\text{V}$ </tex-math></inline-formula> /+3V/+5V. Negative threshold voltage shifts were observed, especially under positive gate biases. It is found out that the threshold voltage shifts are due to the accumulation of positive charges (holes) trapped in the interface of p-GaN/AlGaN. Therefore, the shift amount is proportional to the gate bias and the radiation amount, while not related to the breakdown voltage. After the total ionizing dose experiments, both high temperature and room temperature annealing processes were taken. During the annealing processes, the shifted threshold voltage recovered, and high temperature accelerated the recovery process. Experiment results indicate that the total ionizing dose effect is recoverable.

Electrical Characterization and Modeling of GaN HEMTs at Cryogenic Temperatures

In this work, we present a phenomenological cryogenic model for gallium nitride (GaN) high electron mobility transistors (HEMTs) with validity all the way down to a temperature of 10 K, benchmarked with experimental characterization results. The device under test (DUT) for cryogenic characterization is a GaN HEMT with a channel length of 250 nm and a gate width of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40~\mu \text{m}$ </tex-math></inline-formula> . The characterization results exhibit the negative threshold voltage shifts of −3.437, −3.087, and −2.998 V at the temperatures of 300, 60, and 10 K, respectively. Additionally, kink effects at cryogenic temperatures in output characteristics are observed that behave non-monotonically with gate-to-source bias. The impact of detrapping is modeled to investigate the negative shift in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> with increasing temperature. To model the kink, the effects of temperature, impact ionization, and field-dependent trapping/detrapping on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> have been explored and implemented as a submodel in the industry standard Advanced SPICE Model (ASM)-HEMT framework. Here, we aim to overcome the limitations of the prior GaN device models in the quest for enabling GaN-based circuits for cryogenic applications, such as deep space reception, radio astronomy, and quantum computing.