Negative Setup Time Research Articles

DESIGN OF STANDARD CELL ASIC’S USING SELF GATED RESONANT CLOCKED FLIP FLOP

Efforts to reduce power consumption of digital CMOS circuits have been in progress for nearly three decades. As a result, a number of well understood and proven techniques for reducing dynamic and leakage power have been developed. These methods are implemented thoroughly in the circuit level. So we have to shift our concentration towards high level circuits. One of the example for high level circuit is a standard cell Application Specific Integrated Circuit (ASIC). Reducing the power and delay of standard cell ASIC can improve the performance of the system designed using these. A major contributor to the total power in modern microprocessors is the clock distribution network, which can dissipate as much as 70% of the total power for high performance applications. Self-gated resonant-clocked flip-flop optimized for power efficiency and signal integrity achieves reduced dynamic power dissipation, in addition to the negative setup time, which makes the design more tolerant to the clock skew. This feature also reduces the D-Q delay, thus improving the timing performance of the flip-flop. The advantages of the Self gated resonant clocked flip-flop are implemented on standard cell ASICs. Cadence EDA tools and the 180nm process technology files have been used to substantiate the merits of the proposed design.

Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity

The clock distribution network primarily comprises of the clock tree and the flip-flops. The resonant clocking, which drives a clock tree possesses a large potential for a sweeping power minimisation in the clock network. In addition, the clocked flip-flops, being the crucial timing elements, have become a major contributor to the total power dissipation. Thus, this study proposes a novel ‘self-gated resonant (SGR) clocked flip-flop’ to address these concerns. The proposed flip-flop achieves reduced dynamic power dissipation, in addition to the negative setup time, which makes the design more tolerant to the clock skew. This feature also reduces the D-Q delay, thus improving the timing performance of the flip-flop. Second, this study investigates the use of the resonant clock in a hierarchical clock tree distribution network operating 1024 flip-flops at its leaf nodes. The advantages of the SGR clocked flip-flop are validated through exhaustive simulations and comparisons, with the flip-flop structures available in the literature. Furthermore, the post-layout simulations of a typical H-clock tree driving the 1024 flip-flops at the leaf cells have been carried out. Cadence® EDA tools and the 45 nm process technology files have been used to substantiate the merits of the proposed design.

Low-power pulsed hybrid flip-flop based on a C-element

This paper presents a new flip-flop design featuring implicit pulse-triggered structure in which a dynamic front-end stage and a static back-end one are adopted, thereby, it is considered as a hybrid flip-flop possessing both low-power and high-performance targets. Proposed flip-flop is implemented by a sampling circuit, a C-element for rise and fall paths, and a keeper stage. Simulation results in 45nm CMOS technology with a 1V supply voltage demonstrate that 27.8% and 16.9% reductions in terms of power consumption as compared to all other reported flip-flop designs in 25% and 50% data activities, respectively. Moreover, utilizing only four clocked transistors along with transition condition technique make proposed design fast and power-efficient in all activity factors, and exhibiting 5% enhancement in speed. Hence, other exploitable advantage of presented design is power-delay-product (PDPDQ) index whose improvement ranges from 16.7% to 56%. It is also indicated that presented scheme having negative setup time near zero and considrable hold time contains only 17 transistors severely affecting layout area efficiency being by as much as 12%. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance in power dissipation and PDPDQ metrics.

Low-Power Soft Error Hardened Latch

This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft error on the internal nodes, and transmission gate and Schmitt-trigger circuit to filter out transient resulting from particle hit on combinational logic. The proposed circuit has low power consumption with negative setup time and low timing overhead. The HSPICE post-layout simulation in 90nm CMOS technology reveals that circuit is able to recover from almost any single particle strike on internal nodes and tolerates input SETs up to 130ps of duration.

Novel explicit pulse-based flip-flop for high speed and low power SoCs

In this paper, novel explicit pulse-based flip-flop having dual precharge nodes is presented. Dual precharging can minimize the parasitic capacitance of each precharge node by making output transistors driven separately, resulting in high-speed and low-power operation. The switching speed is further improved by avoiding the use of stacked transistors for driving the output load. Pulse-based nature of the proposed flip-flop also provides a negative setup time and minimizes the effects of clock skew. The proposed flip-flop was designed using a 0.18um CMOS technology, whose comparison results indicate that the flip-flop achieves up to 32% power reduction with 11% speed improvement. They also indicate that the power-delay product is decreased by up to 39% compared to conventional pulse-based flip-flops.

High-performance and low-power conditional discharge flip-flop

In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.

Dual edge-triggered flip-flop with modified NAND keeper for high-performance VLSI

Abstract This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and eliminating redundant transitions. It also minimizes latency by reducing the height of transistor stack on the critical path. In addition, DETNKFF allows negative setup time to provide useful attribute of soft clock edge. Simulation results indicate that the proposed flip-flop reduces power consumption and latency by up to 56% and 28%, respectively, as compared to conventional flip-flops. For the typical input switching activity of 0.3, the power-delay product is also improved by as much as 61%. Synchronous counters were fabricated using a 0.35 μm CMOS technology. Experimental result indicates that the counter with DETNKFF saves overall power consumption by 48% and the layout area by 18% as compared to that with Hybrid latch flip-flop (HLFF).

Conditional-capture flip-flop for statistical power reduction

This paper describes a family of novel low-power flip-flops, collectively called conditional-capture flip-flops (CCFFs). They achieve statistical power reduction by eliminating redundant transitions of internal nodes. These flip-flops also have negative setup time and thus provide small data-to-output latency and attribute of soft-clock edge for overcoming clock skew-related cycle time loss. The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power savings of around 67%, as compared to conventional flip-flops. With a typical switching activity of 0.33, the power consumption is reduced by as much as 23-30% with comparable minimum data-to-output latency. It is also indicated that the proposed single-ended structure provides power comparable to the fully static master-slave design with significantly reduced data-to-output latency. An eight-bit counter was fabricated using a 0.35-/spl mu/m CMOS technology, and the experimental results indicate that the counter using the differential CCFF saves the overall power consumption by about 30% as compared to that using the conventional flip-flop.