Negative Bias Temperature Instability Performance Research Articles

Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-permittivity ( ${\kappa }$ ) metal-gate (HKMG) components into the logic and high-voltage (e.g., I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong NBTI lifetime degradation is observed as soon as high- ${\kappa }$ layers are deposited on top of the thick interfacial layer. In this work, a review of the impact of these high- ${\kappa }$ layers on the NBTI high voltage logic for memory devices is presented. The stress induced degradation is correlated to a diffusion of metal atoms from the HKMG gate stack towards the silicon surface. Directions for reliability improvements are then defined. The presence of Nitrogen throughout the HKMG stack can originate either from high- ${\kappa }$ processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO2 interface region, together with AlOx and/or F incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high- $\kappa $ fluorination and/or cap, metal gate) will be presented. Potential solutions for this reliability challenge will be reported.

Impact of Post High-κ Deposition Anneal (PDA) and Post High-κ Capping Anneal (PCA) on the xBTI Performance in HfO2-Based FinFETs

This paper mainly deals with the impact of high-κ/metal gate (HKMG) module on the xBTI performance in 16/14 nm FinFETs. Both Post high-κ Deposition Anneal (PDA) and Post high-κ Capping Anneal (PCA) are utilized to improve the reliability of HfO2-based FinFETs. The intrinsic correlation between annealing temperature and reliability improvement is systematically investigated. Achieved results show that for p-type FinFETs, both PDA and PCA can improve the Negative Bias Temperature Instability (NBTI) performance, due to the restoration of Si/interfacial layer (IL) interface trap states and IL regrowth. Moreover, NBTI performance is more sensitive to the variation of PDA temperature than PCA temperature. For n-type FinFETs, PDA instead of PCA can improve the Positive Bias Temperature Instability (PBTI) performance, because of oxygen vacancies passivation in the high-κ dielectric bulk and the IL regrowth. Especially, as the increase of PDA temperature, the improvement of PBTI is strengthened.

Treatments for reliability improvement in thick oxides diffusion and gate replacement I/O transistors

In this work, the negative bias temperature instability (NBTI) performance for HKMG and diffusion and gate replacement (D&GR) input/output (I/O) devices is investigated. Even though NBTI performances of D&GR transistors are aligned with conventional HKMG (high-k/metal gate) integration with thin oxide devices, it is not the case for thick oxide I/O devices. In particular, it is shown that strong lifetime degradation is observed as soon as high-k layers are deposited on top of the thick interfacial layer. The NBTI degradation is correlated to a diffusion of Ti/Hf (potentially Al) elements from the HKMG gate stack down to the interfacial layer. Directions for reliability improvement treatments are then defined. It is shown that decoupled plasma nitridation (DPN) and fluorine implant could greatly improve NBTI performance, through an improvement of interface and bulk (inside SiO2 interfacial layer) defect density. Device trade-offs are also investigated for the DPN treatments and fluorine implants cases.

Influence of I/O oxide process on the NBTI performance of 28 nm HfO2-based HKMG p-MOSFETs

The NBTI (negative bias temperature instability) performance of 28nm HfO2-based HKMG (high-κ metal gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (in-situ steam generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (post deposition anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (decoupled plasma nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (electrical oxide thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements.

Negative Bias Temperature Instability for Sputtering Modification in a TiN Diffusion Barrier of p+ Polysilicon Gate Stack in 50-nm DRAM Technology

Negative bias temperature instability (NBTI) in plasma-nitrided oxide affected by the nitrogen incorporation of a TiN diffusion barrier layer of gate stack is first proposed. In the standard 50-nm DRAM technology, three different groups including high, medium, and low N2 flow were deposited by sputtering to investigate in this paper. The high N2 flow group was with higher drive current and higher transconductance, but worse NBTI performance in pMOSFETs than that of the low N2 flow group. Boron (B) concentration at the bottom of p+ polycrystalline silicon (poly-Si) for the high N2 flow group is 5.4% higher than that for the low N2 flow group, which is verified by the secondary ion mass spectroscopy depth profile. A vertical electric field across gate nitrided oxide enhanced by high B concentration in the interface of p+ poly-Si/nitrided oxide resulted in the degradation of NBTI and time-dependent dielectric breakdown of the high N2 flow group. However, process optimization still needs to be studied between device performance and reliability of pMOSFETs in future generation.

SiON Gate Dielectric Optimization for NBTI Improvement

Plasma nitride SiON films have been widely used as gate dielectric in advanced CMOS device fabrication since 90nm technology node. As a replacement material for conventional silicon dioxide, it can provide increased dielectric constant and serve as an effective boron barrier. Post nitridation anneal (PNA), a critical step for plasma nitride SiON formation, is used to stabilize plasma incorporated nitrogen radicals and ions through form thermal stable Si-N banding. Furthermore, PNA can repair the damaged Si/SiO2 interface by interface substrate re-oxidation under oxygen contained ambient. In this work, several PNA conditions were studied. Their effect on transistor performance and PMOS NBTI (Negative Bias Temperature Instability) lifetime were evaluated. It demonstrates that NBTI performance can be improved 20% by PNA process optimizing, while keeping the same Tinv thickness and Ioff/Ion performance.

Forward-Body-Bias-Enhanced Negative Bias Temperature Instability Recovery of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Experimental investigation on the negative bias temperature instability (NBTI) recovery of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) with forward body bias (FBB) was conducted. Our results show that not only the positive gate bias but also the FBB will enhance the recovery of NBTI for pMOSFETs. A forward-body-bias-enhanced NBTI recovery mechanism was proposed with evidence of the NBTI recovery with FBB dependence and corresponding electron/hole density simulation results. Furthermore, the dynamic NBTI degradation was compared with and without FBB. The enhancement of NBTI recovery by FBB gives a comparable lifetime of zero body bias, which indicates that the forward body biasing technique can improve the drive capability without deteriorating NBTI performance.

Negative-bias temperature instability cure by process optimization

Negative-bias temperature instability (NBTI) is a major challenge for modern integrated circuits and may represent a key factor for the success of a technology. In this paper, NBTI is approached from a process point of view, providing a general picture of the manufacturing process steps that affect NBTI performance. It is found that several process steps may be optimized to reduce the NBTI susceptibility of p-type MOSFETs. The choice of the cure approach depends on the device application, on the technology, and also on the equipment.

Optimization of Interlevel Dielectrics for Embedded Nonvolatile Deep Submicrometer Technologies

This paper investigates the requirements that interlevel dielectrics (ILD) and borderless dielectric materials need to fulfil the task of integrating in one chip both double-poly memory and standard single-poly complementary metal oxide semiconductor (CMOS) logic devices. It is found that (i) plasma-enhanced chemical vapor deposition-tetraethylonthosilicate (PECVD-TEOS) (the standard choice for submicrometer logic CMOS ILD deposition) leads to void formation in the memory array. These voids cause bitline-bitline shorts. Voids are suppressed, if high density plasma (HDP) or subatmospheric pressure CVD (SACVD) oxides are used instead. The higher charging and the lower hot-carrier lifetime measured in the case of HDP-deposited wafers indicates SACVD-TEOS with seed layer as the best trade-off between yield and reliability requirements; (ii) the use of SACVD-TEOS as an ILD insulator improves the negative bias temperature instability performance compared to PECVD-TEOS; (iii) borderless SiON films do not ensure the isolation of the memory cell at the high voltages used during the memory write operation. Dual-frequency SiN deposition is required to guarantee a manufacturable bitline to control gate isolation instead.