Negative Bias Temperature Instability Measurements Research Articles

Performance and Reliability Degradation of CMOS Image Sensors in Back-Side Illuminated Configuration

We present a systematic characterization of wafer-level reliability dedicated test structures in Back-Side-Illuminated CMOS Image Sensors. Noise and electrical measurements performed at different steps of the fabrication process flow, definitely demonstrate that the wafer flipping/bonding/thinning and VIA opening proper of the Back-Side-Illuminated configuration cause the creation of oxide donor-like border traps. Respect to conventional Front-Side-Illuminated CMOS Image Sensors, the presence of these traps causes degradation of the transistors electrical performance, altering the oxide electric field and shifting the flat-band voltage, and strongly degrades also reliability. Results from Time-Dependent Dielectric Breakdown and Negative Bias Temperature Instability measurements outline the impact of those border traps on the lifetime prediction.

NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling

We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages and thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast NBTI measurements and an extensive TCAD analysis, we study two physics-based compact models for analog-stress NBTI including recovery. The high accuracy of both models is evidenced from single-FET analog-stress and circuit-level ring oscillator experiments. Their numerical efficiency allows direct coupling to circuit simulators and permits to accurately account for NBTI already during circuit design. Furthermore, one of the models calculates the time-dependent NBTI variability of single-FET and of circuit performance parameters. We demonstrate our NBTI models on a ring oscillator and calculate the mean drift and statistical distribution of its oscillation frequency.

A method for negative bias temperature instability (NBTI) measurements on power VDMOS transistors

A method suitable for performing NBTI measurements on power p-channel VDMOS transistors is described. A practical implementation using simple boosting circuit for obtaining required gate stress voltage and sweep I–V measurements for the threshold voltage shift determination is presented. Experimental results are discussed in terms of the time necessary to perform interim measurements during NBTI tests. It is shown that the measurements could be done fast enough to capture part of the dynamic recovery effect in these devices, which is important for the lifetime prediction.

Essential aspects of Negative Bias Temperature Instability (NBTI)

We develop a comprehensive theoretical framework for explaining the key and characteristic experimental signatures of NBTI. The framework is based on an uncorrelated dynamics of interface-defect creation/annihilation described by Reaction-Diffusion (R-D) theory and hole trapping/detrapping into/out-of oxide defects based on a generalized Shockley-Read-Hall model. The proposed theory can consistently explain the long-term stress-phase power-law time exponent, stress/relaxation-phase temperature dependence, characteristic feature of duty-cycle dependence, and universal feature of frequency independence - measured in DC and AC stress conditions over a wide variety of transistors. Thus, we confirm the general validity of R-D theory in explaining the universal features (irrespective of dielectric material) of both DC and AC NBTI. The non-universal features of NBTI have correlation with the amount of oxide-defects within the dielectric and do not affect AC NBTI measurements at lower duty cycle. Decomposition of these (uncorrelated) universal and non-universal components is, therefore, essential before comparison with any theory.

Competing Charge Relaxation Mechanisms in HfSiON Insulator Field Effect Transistors

We present negative bias temperature instability (NBTI) charge stress data, taken on 1 um HfSiON MOSFETs, which suggests the existence of an NBTI relaxation mechanism not previously reported in the literature. In particular, we observe significantly less NBTI damage in devices stressed in the MOSFET saturation region (large Vds) than in those stressed in the linear region (small Vds). We propose that this observation is explained by transport of trapped positive charge parallel to the channel, but inside the insulator, perhaps along a high defect density region in the HfSiON. This observation has interesting and important implications for high-k materials studies and NBTI measurement protocols.

A New Fast-Switching NBTI Characterization Method That Determines Subthreshold Slope Degradation

For PMOSFET devices, negative bias temperature instability (NBTI) is a serious reliability concern. Because of recovery effects, careful stress and measurement methods must be used to determine threshold voltage degradation. These methods typically assume that mobility and subthreshold slope (SubSlp) degradation are minimal. Recent papers have pointed out that this assumption may not be valid. This paper discusses for the first time a unique fast-switching NBTI measurement technique that alternates between two VGS measurement conditions to determine the SubSlp versus stress time. From these measurements, the effect of SubSlp degradation on VT degradation can be accurately determined, and results are compared to the standard techniques.

Negative-Bias Temperature Instability: Measurement and Degradation Mechanisms

This paper addresses two important aspects of negative-bias temperature instability (NBTI), namely measurement methodology and degradation mechanisms. An improved ultra-fast switching measurement method with sub-100 ns delay is presented. The method is based on customary pulsed current-voltage equipment and thus provides an attractive standard for NBTI measurement. Both linear and subthreshold drain current measurements are discussed and the relevant limitations addressed. In the discussion, it is shown that the gate voltage shift extracted through the computation of integral (dId,lin/gm) grossly over-estimates the threshold voltage shift |DVt| (i.e. the fraction of gate voltage shift due to interfacial trapped charge) because of mobility degradation. Ignoring this effect results in an unduly pessimistic assessment of interfacial trapped charge generation. We propose a better method that could delineate both |DVt| and low-field mobility degradation. In addition, results which indicate two distinct degradation mechanisms are presented. Experimental evidence that shows a "bipolar" (i.e. both acceptor- and donor-like) characteristic of stress induced interface traps is discussed. Finally, features of dynamic NBTI which do not conform to the reaction-diffusion model are highlighted.

Contribution of Interface States and Oxide Traps to the Negative Bias Temperature Instability of High-$k$ pMOSFETs

Negative bias temperature instability (NBTI) in MOSFETs with high-dielectric-constant (k) gate dielectrics has been investigated using a novel pulse NBTI measurement technique. This technique enabled the separation of the contribution of interface states (N it) from that of oxide traps (N ot) to NBTI behavior by varying the measurement time (t m) and the delay time (t R). The technique was demonstrated on devices fabricated with different postdeposition annealing (PDA) conditions. It was found that, regardless of the PDA condition, the N ot in high-k dielectric was more responsible for the NBTI behavior than the N it, but the contribution of N it to NBTI increased as the stress continued because the generation rate of N it was higher than that of N ot.

Reliability of Strained-Si Devices With Post-Oxide-Deposition Strain Introduction

To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high-kappa and FUSI/high-kappa gate stacks. The effects of compressive stress, which acts as performance booster for PMOS devices, were studied, with strain introduced by stressor layers as well as SiGe source/drain techniques. Care was taken to account for side effects of processing steps used to introduce the strain, such as changes on threshold voltage or capacitance equivalent thicknesses, in order to obtain a fair evaluation of the intrinsic effect of strain on NBTI. NBTI measurements were complemented by charge pumping and noise measurements to obtain a comprehensive understanding of defects present and of their generation under stress. In addition, nanobeam diffraction strain measurements, as well as curvature mass simulations, were performed in order to investigate the impact of strain on carrier mobility in the vertical direction. Our studies showed consistently that there is no significant degradation of intrinsic NBTI behavior due to process-induced strain.

Critical analysis of short-term negative bias temperature instability measurements: Explaining the effect of time-zero delay for on-the-fly measurements

Recently several groups have used the reaction-diffusion (R-D) model with H2 diffusion in interpreting negative bias temperature Instability (NBTI) degradation. While the classical “H2 R-D” model can interpret long-term NBTI behavior, it is inconsistent with short-term stress data obtained by recently developed ultrafast measurements and widely used on-the-fly measurements. Moreover, experimental data from various techniques are not consistent with each other. Here, the authors show that the H2 R-D model must be generalized to consistently interpret NBTI at all time scales. The generalized model highlights the previously unappreciated role of time-zero delay in reconciling differences among the so-called delay-free on-the-fly measurements.

Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design.

Reliability and Stability Issues for Lanthanum Silicate as a High-K Dielectric

Lanthanum silicate gate dielectric MIS devices have been studied in relation to material stability and device reliability. Uncapped dielectric films 2 nm thick exposed to air for 7 months show very little increase in hydroxide formation (~2%, determined by XPS) if experiencing an initial high temperature anneal (1000{degree sign}C, 10 sec). Likewise, after an initial 1000{degree sign}C anneal, MIS device characteristics show no appreciable change over this time period. Negative bias temperature instability measurements on MIS devices at 100{degree sign}C and -2.5 V reveal process-temperature-dependent midgap voltage shifts, with negative shifts (>50 mV) observed for <=900{degree sign}C processing indicating predominantly hole trapping, and small (10 mV) positive shifts for samples experiencing a 1000{degree sign}C process temperature, well within accepted device reliability limits. These results indicate that lanthanum silicate will not introduce significant device lifetime issues when optimally processed.

Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric

New findings of interface trap passivation effect in negative bias temperature instability (NBTI) measurement for p-MOSFETs with SiON gate dielectric are reported. We show evidence to clarify the recent debate: the recovery of V/sub th/ shift in the passivation phase of the dynamic NBTI is mainly due to passivation of interface traps (N/sub it/), not due to hole de-trapping in dielectric hole traps (N/sub ot/). The conventional interface trap measurement methods, dc capacitance-voltage and charge pumping, seriously underestimate the trap density N/sub it/. This underestimation is gate bias dependent during measurement, because of the accelerated interface trap passivation under positive gate bias. Due to this new finding, many of previous reliability studies of p-MOSFETs should be re-investigated.

Dynamic recovery of negative bias temperature instability in p-type metal–oxide–semiconductor field-effect transistors

An unexpected physical phenomenon—dynamic recovery of negative bias temperature instability (NBTI)—is reported. NBTI degradation in p-type metal–oxide–semiconductor field-effect transistors is significantly (by ∼40%) reduced after stress interruption. NBTI recovery dynamics includes a very fast transient (seconds time scale) followed by a slow (tens of minutes) transient, which tends to saturate. Under subsequent application of stress bias, the degradation quickly returns to its previous state. Thus, apparent NBTI degradation includes permanent and reversible components. NBTI degradation and device lifetime depend strongly on the measurement procedure and equipment due to these relaxation phenomena, which should be taken into account in analyzing the results of NBTI measurements.