Negative Bias Temperature Instability Behavior Research Articles

A physics-based TCAD framework for NBTI

A physics-based framework is incorporated in TCAD to model the primary mechanisms responsible for Negative Bias Temperature Instability (NBTI) in P channel High-K Metal Gate (HKMG) MOSFETs. Three underlying mechanisms are treated including interface trap generation-passivation via a Reaction-Diffusion (RD) model and its charge occupancy via an Activated Barrier Double Well Thermionic (ABDWT) model, hole trapping and de-trapping in pre-existing defects in the gate stack are modeled via an ABDWT model, and bulk trap generation-passivation is modeled via a Reaction-Diffusion-Drift (RDD) model. The framework is used to model measured NBTI time-kinetics for DC stress-recovery and various mixed DC-AC gate pulse segments for planar devices. Furthermore, the same framework is also used to test NBTI behavior in 3D FinFETs.

7‐1: Distinguished Paper: Alleviation of Abnormal NBTI Phenomenon in LTPS TFTs on Polyimide Substrate for Flexible AMOLED

This letter investigates the negative‐bias temperature instability (NBTI) behavior of p‐channel low‐temperature polycrystalline silicon thin‐film transistors (LTPS TFTs) on plastic substrate. The measurements reveal that the threshold‐voltage positive shift is highly correlated to the passivation of grain‐boundary trap states. By applying the established phenomenon such as NBTI recovery and H diffusion from PI substrate, a new model is introduced to explain mechanism and verified by the experiment. With the thick buffer & bottom metal layer or newly processed PI substrate, we succeeded in adjusting the NBTI behavior of LTPS TFTs on plastic substrate.

Alleviation of abnormal NBTI phenomenon in LTPS TFTs on polyimide substrate for flexible AMOLED

AbstractThis letter investigates the negative‐bias temperature instability (NBTI) behavior of p‐channel low‐temperature polycrystalline silicon thin‐film transistors (LTPS TFTs) on plastic substrate. The measurements reveal that the threshold‐voltage positive shift is highly correlated to the passivation of grain boundary trap states. By applying the established phenomenon such as NBTI recovery and H diffusion from PI substrate, a new model is introduced to explain the mechanism and verified by the experiment. With the thick buffer and bottom metal layer or newly processed PI substrate, we succeeded in adjusting the NBTI behavior of LTPS TFTs on plastic substrate.

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.

Statistical forecasting algorithm on circuit level gain transformation due to negative bias temperature instability for the microwave frequency spectrum

Negative Bias Temperature Instability (NBTI) is a critical reliability issue for CMOS technology, as this directly impacts the CMOS circuit performance parameters causing system failure. Moreover, NBTI behavior for radio frequency (RF) signals needs more understanding. On the device level, there has been much research on the relation between NBTI and RF. Many of those works contradict each other on the question of RF dependency with NBTI. Hence, the behavior of NBTI must be analyzed at the circuit level using a prediction technique. In this article, we analyzed the circuit level impact of NBTI for microwave frequency and developed a gain transformation technique for RF circuits in the microwave frequency range. To do this, we employed a 65 nm conventional ring oscillator as an RF block and carried out an aging simulation on it. A compatibility analysis was performed on low and high bandwidth microwave signals. The implemented statistical technique can determine the actual operable frequency range, so that the RF circuit can perform with minimal NBTI effect.

HCI and NBTI induced degradation in gate-all-around silicon nanowire transistors

The silicon nanowire transistor (SNWT) with gate-all-around (GAA) structure can be considered as one of the potential candidates for ultimate scaling due to its superior gate control capability and improved carrier transportation property. In this paper, hot carrier injection (HCI) and negative bias temperature instability (NBTI) behavior of n-type and p-type SNWTs with top-down approach is discussed. In addition to initial fast degradation and quick saturation of NBTI stress behavior, non-negligible impacts of electron traps on the stress/recovery characteristics in p-SNWTs with metal gate is found and characterized with a kind of combined Ig–Id RTN technique. The NBTI behavior is modeled taking account of the impacts from unique structural nature of GAA SNWTs. NBTI induced performance degradation of the typical nanowire-based circuits is estimated based on the proposed model. In addition, stochastic degradation induced by single/few trap in the thin-body SNWTs is observed and analyzed.

Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging

In this paper, the negative-bias temperature instability (NBTI) in p-type gate-all-around silicon nanowire MOSFETs (SNWTs) is investigated for circuit aging analysis. Several important features of NBTI in SNWTs are discussed, including the impacts of 2-D hydrogen diffusion, the nonuniform temperature profile caused by self-heating effects, the multiple crystallographic orientations of nanowire channel surface, the gate-trimming process-induced additional trapping effects, and the impacts of oxide hole trapping. A predictive NBTI model for SNWTs is proposed and adopted in circuit simulation to evaluate the performance degradations of typical logic and analog circuits, such as inverter, static random access memory cell, ring oscillator, and current mirror. Without considering other indirect factors, the results indicate that the performance degradation directly due to NBTI alone is relatively small, i.e., within the range of less than 8% degradation for the typical circuits simulated. However, the NBTI behavior in SNWTs is sensitive to process variations, which cause enhanced variability problem by inducing time-dependent threshold voltage fluctuations.

Contribution of Interface States and Oxide Traps to the Negative Bias Temperature Instability of High-$k$ pMOSFETs

Negative bias temperature instability (NBTI) in MOSFETs with high-dielectric-constant (k) gate dielectrics has been investigated using a novel pulse NBTI measurement technique. This technique enabled the separation of the contribution of interface states (N it) from that of oxide traps (N ot) to NBTI behavior by varying the measurement time (t m) and the delay time (t R). The technique was demonstrated on devices fabricated with different postdeposition annealing (PDA) conditions. It was found that, regardless of the PDA condition, the N ot in high-k dielectric was more responsible for the NBTI behavior than the N it, but the contribution of N it to NBTI increased as the stress continued because the generation rate of N it was higher than that of N ot.

Reliability of Strained-Si Devices With Post-Oxide-Deposition Strain Introduction

To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high-kappa and FUSI/high-kappa gate stacks. The effects of compressive stress, which acts as performance booster for PMOS devices, were studied, with strain introduced by stressor layers as well as SiGe source/drain techniques. Care was taken to account for side effects of processing steps used to introduce the strain, such as changes on threshold voltage or capacitance equivalent thicknesses, in order to obtain a fair evaluation of the intrinsic effect of strain on NBTI. NBTI measurements were complemented by charge pumping and noise measurements to obtain a comprehensive understanding of defects present and of their generation under stress. In addition, nanobeam diffraction strain measurements, as well as curvature mass simulations, were performed in order to investigate the impact of strain on carrier mobility in the vertical direction. Our studies showed consistently that there is no significant degradation of intrinsic NBTI behavior due to process-induced strain.

Development of an Ultrafast On-the-Fly $I_{\rm DLIN}$ Technique to Study NBTI in Plasma and Thermal Oxynitride p-MOSFETs

An ultrafast on-the-fly technique is developed to study linear drain current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DLIN</sub> ) degradation in plasma and thermal oxynitride p-MOSFETs during negative-bias temperature instability (NBTI) stress. The technique enhances the measurement resolution (ldquotime-zerordquo delay) down to 1 mus and helps to identify several key differences in NBTI behavior between plasma and thermal films. The impact of the time-zero delay on time, temperature, and bias dependence of NBTI is studied, and its influence on extrapolated safe-operating overdrive condition is analyzed. It is shown that plasma-nitrided films, in spite of having higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> density, are less susceptible to NBTI than their thermal counterparts.

Influence of Nitrogen on Negative Bias Temperature Instability in Ultrathin SiON

Negative bias temperature instability (NBTI) and its recovery phenomenon in ultrathin silicon oxynitride (SiON2) films were investigated. To discuss the influence of nitrogen incorporation into silicon dioxide films, we used NO-nitrided SiON and plasma-nitrided SiON. As a result, it was found that the recovery for plasma-nitrided SiON is less marked than that for NO-nitrided SiON, although NBTI can be suppressed by plasma nitridation. It is also experimentally confirmed that hydrogen plays an important role in these phenomena. On the basis of these results, we proposed nitrogen-originated NBT degradation involving hydrogen at SiON/Si interface and hole trapping/detrapping. Furthermore, NBTI under ac stress was investigated. Not only NBTI was more suppressed under ac stress than under dc stress as already reported, but also, this behavior of dynamic NBTI is independent of nitrogen distribution in SiON.

Anomalous negative bias temperature instability behavior in p-channel metal-oxide-semiconductor field-effect transistors with HfSiON∕SiO2 gate stack

In this letter, the authors systematically investigated the behavior of negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with HfSiON∕SiO2 gate stack. They found that typical linear extrapolation does not work well for the lifetime extraction at the normal operation conditions since the polarities of the net trapped charge inside the high-κ dielectrics are not the same at lower and higher stress voltage regimes. In other words, as ∣Vg∣&amp;lt;2.5V electron trapping dominated while hole trapping dominated when ∣Vg∣&amp;gt;2.5V. This phenomenon obviously contradicts the essence of the linear prediction in which the same degradation mechanism is assumed through the entire stress voltage range.

Improvement in Mobility and Negative-Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with Atomic-Layer-Deposited Si–Nitride/SiO2 Stack Dielectrics

Carrier mobility and negative-bias temperature instability (NBTI) characteristics were studied for p+ polycrystalline Si-gated metal–oxide–semiconductor field-effect transistors (MOSFETs) with various gate dielectrics: atomic-layer-deposited (ALD) Si–nitride/SiO2 stack, plasma-nitrided SiON, and pure-SiO2 dielectrics. MOSFETs with the ALD Si–nitride/SiO2 stack dielectrics offer the lowest interface trap density and highest carrier mobility among the three samples owing to their superior ability to suppress boron penetration. P-channel MOSFETs with the ALD stack dielectrics exhibit an abnormal NBTI behavior: threshold voltage shift (ΔVth) is positive at the early stress stage and then becomes negative at longer stress times. Such a turnaround behavior may be attributed to the presence of preexisting neutral electron traps in the Si–nitride/SiO2 stack dielectrics, which may lead to the net ΔVth of the stack dielectrics stressed at a low voltage to be even smaller than that of the pure-SiO2 dielectrics. The above-mentioned findings suggest that the ALD Si–nitride/SiO2 stack dielectrics are very promising for sub-0.1-µm MOSFETs.

Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior

In this letter, we investigate the effects of process-induced strain on negative bias temperature instability (NBTI) by performing a comparative study of devices with and without process-induced strain for poly-Si/SiON gate stacks. Devices with SiGe source/drain with different processing sequences and devices with a combination of SiGe S/D and compressive contact etch stop layer (CESL) were studied and compared to reference devices. We decouple the effect of processing conditions in order to ensure a correct interpretation of the results. In contrast with the previous reports, which did not consider the impact of processing conditions, this letter demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with a process-induced strain. In addition, we performed an Arrhenius study showing similar activation energies for devices with and without process-induced strain, suggesting similar degradation mechanism. The results indicate that process-induced strain does not create favorable conditions for additional interface state creation

NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase

In this work, we investigate the negative bias temperature instability (NBTI), when Ni-rich (Ni 2Si and Ni 31Si 12) silicides are used as gate electrodes on HfSiON and compare them to Ni mono-silicide (NiSi). The study also investigates the influence of increased pre-metal deposition (PMD) temperature and decreased silicide thickness on NBTI. Our study demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant differences in intrinsic NBTI behavior are found for devices with different Ni silicide gate electrodes. In addition, we performed an Arrhenius study showing similar activation energies, indicating that no favorable conditions for dielectric degradation are created by the increased amount of Ni.

Critical analysis of short-term negative bias temperature instability measurements: Explaining the effect of time-zero delay for on-the-fly measurements

Recently several groups have used the reaction-diffusion (R-D) model with H2 diffusion in interpreting negative bias temperature Instability (NBTI) degradation. While the classical “H2 R-D” model can interpret long-term NBTI behavior, it is inconsistent with short-term stress data obtained by recently developed ultrafast measurements and widely used on-the-fly measurements. Moreover, experimental data from various techniques are not consistent with each other. Here, the authors show that the H2 R-D model must be generalized to consistently interpret NBTI at all time scales. The generalized model highlights the previously unappreciated role of time-zero delay in reconciling differences among the so-called delay-free on-the-fly measurements.

NBTI Study on PMOS Devices with TiN/HfO2 Gate Stack and Process Induced Strain

We investigate the effect of process induced strain on Negative Bias Temperature Instability (NBTI) for devices with TiN/HfO2 gate stacks. Devices with compressive Contact Etch Stop Layer (CESL), SiGe Source/Drain, and devices with a combination of both SiGe and CESL were studied and compared to reference devices. We decouple the effect of processing conditions in order to assure correct interpretation of the results. Our study demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with process induced strain. In addition, we performed an Arrhenius study showing that Si-H bonds under strain exhibit similar activation energies as Si-H bonds without strain, indicating that no favorable conditions for interface states generation are created by the strain.

Device Characteristics and Aggravated Negative Bias Temperature Instability in p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Uniaxial Compressive Strain

P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) featuring poly-SiGe gates and compressive strain channels were investigated. The compressive strain in the channel was deliberately induced in this study by a plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) capping layer over the gate. Our results indicate for the first time that, while strain channel engineering serves as an effective method to enhance drive current for scaled complementary metal–oxide–semiconductor (CMOS) devices consistent with literature reports, it also simultaneously aggravates the negative bias temperature instability (NBTI) of scaled devices. The aggravated NBTI behavior is ascribed to a higher amount of hydrogen incorporation during SiN deposition as well as a higher strain energy stored in the channel. Saturation phenomena in the shift of threshold voltage and generation of interface states are observed at high stress temperatures and long stress times. Moreover, transconductance degradation in devices with SiN capping is greatly aggravated under high temperature stress.

On the non-Arrhenius behavior of negative-bias temperature instability

Evidence from negative-bias temperature stressing of the ultrathin Si3N4∕SiOx gate p-channel field-effect transistor indicates that non-Arrhenius behavior is a consequence of the superposition of two distinct defect generation mechanisms with different power-law time dependence (tn) and activation energy (Ea). The two mechanisms are (1) a hole trapping mechanism (t0.1; Ea∼0.02eV) and (2) the classical hydrogen diffusion mechanism (t0.25; Ea∼0.2–0.3eV). When temperature increases, the latter gradually dominates, causing the exponent n, of the overall time-dependent shift of the device threshold voltage (∣ΔVth∣1+2∝tn), to increase. Eliminating the contribution of the hole trapping mechanism, i.e. ∣ΔVth∣1 from overall threshold voltage shift consistently reproduces ∣ΔVth∣2∝tn characteristics which bear the classical signature of negative-bias temperature instability, i.e., n≈0.25 and is independent of temperature.