Near-interface Oxide Trap Research Articles

Characterization of Near-Interface Oxide Trap Density in Nitrided Oxides for Nanoscale MOSFET Applications

This paper presents the depth profile of oxide trap density, extracted from the dual gate processed thermally grown oxide in NO ambient and remote plasma nitrided oxides by using multifrequency and multitemperature charge pumping technique in conjunction with the tunneling model of trapped charges. Nitrided oxide is widely used to improve the reliability of nanoscale MOSFETs because it can decrease the degradation of gate oxide due to the generation of traps therein. Based on the measurement, the optimum nitrogen concentration in such typical nitrided process is discussed in correlation with the gate oxide thickness for nanoscale CMOSFETs.

High-Field Degradation of Poly-Si Gate p-MOS and n-MOS Devices With Nitrided Oxides

In this paper, the authors investigate polysilicon gate MOS capacitors and MOSFET devices with nitrided oxides. These devices are known to also show a strong negative bias temperature instability (NBTI) effect. The authors analyze the dependence of oxide-trap generation in p-channel and n-channel devices on negative and positive Fowler-Nordheim (FN) charge injection stress by application of various C-V and charge pumping (CP) measurement methods yielding information on traps at different oxide locations. In the case of p-channel devices, a strong evidence for a preexistent very high oxide-trap concentration near the gate already before stress application is obtained. This feature is accompanied by a fast degradation of the p-channel devices under a negative bias stress similar to NBTI degradation. The CP measurements, which, in contrast to classical methods, are able to distinguish between actually fast interface traps and the slower near-interface oxide traps (NIOTs), showed that in all devices, a stress polarity dependence of trap generation occurs only for NIOTs and not for interface traps

Abnormal enhancement of interface trap generation under dynamic oxide field stress at MHz region

By stressing metal-oxide-semiconductor field-effect transistors with ultrathin silicon dioxide or oxynitride gate dielectrics under square wave form voltage at the MHz region, an abnormal enhancement of interface trap generation in the midchannel region has been observed at some special frequencies. A hypothesis, including self-accelerating interface trap generation originated from the positive feedback of a charge pumping current to be contributed by the stress-induced near-interface oxide traps and a resonant tunneling via the near interface oxide trap states at those frequencies, is proposed to explain the observed phenomenon.

Identification of isolation-edge related random telegraph signals in submicron silicon metal–oxide–semiconductor field-effect transistors

In this letter, evidence is given for a new class of random telegraph signals (RTSs) in submicron n-metal–oxide–semiconductor field-effect transistors (n-MOSFETs). These two-level fluctuations not only occur when the MOSFET is biased in linear operation but also when it is operated in the source or drain-substrate diode mode. A detailed investigation of the RTS parameters, i.e., the amplitude, the emission, and the capture time constants, reveal a close correlation with the current through the forward biased drain- (or source-) substrate diode. At the same time, from the substrate bias dependence of the trap characteristics, it is inferred that it behaves like a near-interface oxide trap. From this, it is concluded that the most likely position is along the channel width perimeter, at the isolation edges of the transistors and close to the source or drain junction.

Quantum two-dimensional calculation of time constants of random telegraph signals in metal-oxide–semiconductor structures

The thermal and gate-voltage dependencies for the capture and emission times of random telegraph signals have been theoretically analyzed in a ${\mathrm{S}\mathrm{i}\ensuremath{-}\mathrm{S}\mathrm{i}\mathrm{O}}_{2}$ interface. A quasi-two-dimensional treatment of the interaction between a neutral near-interface oxide trap and an electron in the subband of the inversion layer has been developed to obtain expressions for the capture and emission times where the influence of the trap parameters (energy depth, distance to the interface, and electron-phonon coupling factor) is clearly shown. This analysis combines multiphonon-emission theory, tunnel transition probability and the electrostatic Coulomb barrier effect, allowing us to reproduce experimental data for traps in different devices, temperatures, and bias conditions. As a result, trap distances to the interface, trap energy levels, and electron-phonon couplings have been calculated. The character of single electron transitions in this process let us show that the ground and first excited subbands, with similar capture and emission times, are the most important contributors to the phenomenon.

Observation and characterization of near-interface oxide traps with C-V techniques

The anomalous hump observed in low frequency C-V curves of stressed devices is attributed to near-interface oxide traps, rather than so-called "interface" traps. A low frequency C-V model has been developed to interpret the effect of near-interface oxide traps which communicate with the Si-SiO/sub 2/ interface traps and influence C-V characteristics. At low measurement frequencies, electrons have sufficient time to tunnel from interface traps and fill near-interface oxide traps via a trap-to-trap tunneling mechanism. By varying the measurement frequency, a spatial distribution of near-interface oxide traps is obtained. A consistent near-interface oxide trap distribution has been extracted for a trap-rich SONGS memory transistor using both variable frequency Hi-Lo C-V and charge pumping techniques.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Random telegraph signals in silicon-on-insulator metal-oxide- semiconductor transistors

Possible physical mechanisms for random telegraph signal (RTS) -like fluctuations in the front-channel drain current of a silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) transistor are discussed. Particular emphasis is on two RTS mechanisms which are believed to be typical for a SOI MOS transistor. The first one is related to carrier trapping in the Si film, by a deep-level trap in the depletion region. As such, this type of RTS is more or less complementary to the standard behavior, which is caused by carrier trapping through a near-interface oxide trap. Second, it is demonstrated experimentally that by varying the back-gate bias of a thin-film SOI MOS transistor ‘‘new’’ RTSs may be detected.

New insight into high-field mobility enhancement of nitrided-oxide N-MOSFET's based on noise measurement

The mobility crossover phenomenon observed in NH/sub 3/-nitrided N-MOSFET's has been interpreted by the reduced acceptor-type interface states which are located near and above the conduction band edge. However. A direct confirmation of such a hypothesis is not available from the conventional electrical measurement techniques. In this work, for the first time, we used both 1/f noise and random telegraph signal (RTS) measurements which are capable of probing those oxide traps near and above Si conduction band of energy, to study the modification of interface traps induced by N/sub 2/O nitridation. The 1/f noise measurement results confirm that thermal nitridation decreases the near-interface oxide trap density at the higher energy levels, as a result, trapping of the mobile electrons is decreased. The RTS measurement further suggests that thermal nitridation moves the oxide traps farther away from the Si-SiO/sub 2/ interface and thus suppresses the Coulombic scattering of mobile electrons by the trapped charges. Both nitridation-induced interfacial modifications result in enhanced high-field mobility of nitrided-oxide devices over the standard MOS devices. >