NB-LDPC Decoder Research Articles

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10^{-3}.

ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.

An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination

This paper presents a modified Trellis Min-Max (T-MM) algorithm together with the associated architecture for non-binary (NB) low-density parity-check (LDPC) decoders. The proposed T-MM algorithm is able to reduce the memory requirements for the check-node messages through an efficient compression method and enhance the error-rate performance using the appropriate decompression. A method of updating the a posteriori log-likelihood ratio in the delta domain is used to simplify the computational and storage complexity. In order to enhance the decoding throughput, a low-complexity early termination (ET) scheme is devised by using the hard decisions of the variable-to-check messages, where, although a minor overhead is introduced, there is no visible degradation in error rate. As a proof of concept, a row-parallel layered decoder for the 32-ary (837, 726) LDPC code is implemented using a 90-nm CMOS process. The proposed decoder achieves a throughput of 1.64 Gb/s at 526.32 MHz based on eight iterations and has an area of 6.86 mm 2 . When the ET scheme is enabled, the decoder achieves a maximum throughput of 4.68 Gb/s with a frame error rate of 3.25 x 10^-6 at E_b/N_0 = 4.5 dB. The proposed NB-LDPC decoder achieves the highest throughput and hardware efficiency compared to the state-of-the-art decoders, even when the ET scheme is not enabled.

High throughput and low complexity implementation of NB-LDPC decoder based on EMS algorithm

High throughput and low complexity implementation of NB-LDPC decoder based on EMS algorithm

Application of bubble‐check algorithm to non‐binary LLR computation in QAM coded schemes

The generation of intrinsic LLR messages in non-binary (NB) coded schemes associated with quadrature amplitude modulation (QAM) is considered. It is shown that the intrinsic LLR message generation corresponds to the same kind of computation as the one performed at the elementary check nodes in extended min-sum NB-LDPC decoders, i.e. finding a given number of minimum values in a structured set. It is proposed to use the bubble-check algorithm for the LLR calculation to benefit from two advantages: low-complexity hardware architecture and sharing the same hardware at the demapping and the decoding steps.

Performance Analysis and Implementation for Nonbinary Quasi-Cyclic LDPC Decoder Architecture

Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity iterative decoding algorithms have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high complexity and long latency. In this brief, highly efficient check node processing scheme, which the processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are proposed. Compare with previous works, less than 52% could be reduced for the latency of check node unit. In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NBQC-LDPC decoder.

Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes

Compared to binary low-density parity-check (LDPC) codes, nonbinary (NB) LDPC codes can achieve higher coding gain when the codeword length is moderate, but at the cost of higher decoding complexity. One major bottleneck of NB-LDPC decoding is the complicated check node processing. In this paper, a novel relaxed check node processing scheme is proposed for the min-max NB-LDPC decoding algorithm. Each finite field element of GF(2p) can be uniquely represented by a linear combination of p independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then, the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and the overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(25) can achieve 52% higher efficiency in terms of throughput-over-area ratio.

Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes

This paper presents a block-layered decoder architecture and efficient design techniques for quasi-cyclic nonbinary low-density parity-check (QC-NB-LDPC) codes. Based on a Min-Max decoding algorithm, an efficient block-layered decoder architecture for QC-NB-LDPC codes is proposed for fast decoder convergence. Further, a novel two-way merging Min-Max algorithm, which significantly reduces decoding latency, is proposed for check node processing. The NB-LDPC decoder using the proposed algorithm can provide a considerably higher throughput rate than that using a conventional Min-Max algorithm. The proposed (225, 165) NB-LDPC decoder over GF(24) is synthesized using a 90-nm CMOS process. It can operate at a clock rate of 400 MHz and achieve a data processing rate of 24.6 Mbps under 10 decoding iterations.

Iterative Multi-Track ITI Canceller for Nonbinary-LDPC-Coded Two-Dimensional Magnetic Recording

An iterative inter-track interference (ITI) cancelling scheme is described for multi-track signal detection in nonbinary (NB)-LDPC-coded two-dimensional magnetic recording. The multi-track iterative ITI canceller that we propose consists of multi-track soft interference cancellers (SICs), two-dimensional partial response (TDPR) filters, noise-predictive max-log-MAP detectors, and an NB-LDPC decoder. TDPR filters using an ITI-suppressing tap-weight vector mitigate ITI in the first iteration. Multi-track SICs and TDPR filters adjusted to the residual two-dimensional ISI signals efficiently detect multi-track signals in the latter iterations. The simulation results demonstrated that our proposed iterative multi-track ITI canceller achieves frame error rates close to those obtained in a non-ITI case in media-noise-dominant environments when the both-side off-track ratio is up to 50%.