The dielectric degradation phenomena in gate oxides of MoSi <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /thin n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> poly-Si (<100 nm) gate structure which appeared after high-temperature annealing have been analyzed in detail. Analyses included obtaining the correlation between gate oxide dielectric characteristics and various factors like phosphorus concentration in poly-Si, native oxide on poly-Si, sheet resistance of MoSi <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the SEM or TEM observations of textures of MoSi <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , poly-Si, and gate oxide. From analyses, it was concluded that the local reaction of molybdenum silicide with poly-Si under the presence of a barrier, like the thick native oxide on poly-Si formed before MoSi <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> deposition, results in the damage to a gate oxide through a thin poly-Si layer during annealing. Based upon analytical results, a new MoSi <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /thin poly-Si gate process without dielectric degradation has been developed, in which the direct MoSi <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> deposition on undoped poly-Si to suppress the native oxide growth and phosphorus implantation into MoSi <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> were introduced. The process provided a good dielectric strength of a gate oxide even to the device with a poly-Si layer as thin as 50 nm, an easy dry etching without undercutting of poly-Si, and stable device characteristics and reliabilities compatible to a conventional poly-Si gate process.